library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity trg_emulator is
  generic (
    cnt_width : integer := 10
  );

  port (
    clk40 : in std_logic;
    rst40 : in std_logic;

    pt_in : in std_logic;
    l0_in : in std_logic;
    l1_in : in std_logic;

    pt_out : out std_logic;
    pt_ctp : out std_logic;
    l0_out : out std_logic;
    l1_out : out std_logic;

    trg_delay : in std_logic_vector(cnt_width-1 downto 0) := conv_std_logic_vector(48, cnt_width)
  );

end trg_emulator;

architecture behav of trg_emulator is

  signal cnt_after_ptrg    : std_logic_vector(cnt_width-1 downto 0);
  signal cnt_delay_l0      : std_logic_vector(cnt_width-1 downto 0);
  signal cnt_delay_l1      : std_logic_vector(cnt_width-1 downto 0);

  signal pre_miss : std_logic;

  signal l0_delayed : std_logic;
  signal l1_delayed : std_logic;

  constant ones : std_logic_vector(cnt_width-1 downto 0) := (others => '1');

begin

  pre_miss <= '1' when (cnt_after_ptrg >= trg_delay) else '0';

  process (clk40, rst40)
  begin
    if (rst40 = '1') then
      pt_out <= '0';
      l0_out <= '0';
      l1_out <= '0';
      cnt_after_ptrg <= (others => '1');
      cnt_delay_l0  <= (others => '1');
      cnt_delay_l1  <= (others => '1');
      l0_delayed <= '0';
      l1_delayed <= '0';
      pt_ctp <= '0';

    elsif rising_edge(clk40) then
      pt_out <= '0';
      pt_ctp <= '0';
      l0_out <= '0';
      l1_out <= '0';

      if (cnt_after_ptrg /= ones) then
        cnt_after_ptrg <= cnt_after_ptrg + 1;
      end if;

      if (cnt_delay_l0 /= ones) then
        cnt_delay_l0 <= cnt_delay_l0 + 1;
      end if;

      if (cnt_delay_l1 /= ones) then
        cnt_delay_l1 <= cnt_delay_l1 + 1;
      end if;

      if (pt_in = '1') then
        pt_out <= '1';
        pt_ctp <= '1';
      end if;

      if (l0_in = '1') then
        if (pre_miss = '1') then
          pt_out <= '1';
          l0_delayed <= '1';
          cnt_delay_l0 <= (others => '0');
        else
          l0_out <= '1';
          l0_delayed <= '0';
        end if;
      end if;

      if (l1_in = '1') then
        if (l0_delayed = '1') then
          l1_delayed <= '1';
          cnt_delay_l1 <= (others => '0');
        else
          l1_out <= '1';
          l1_delayed <= '0';
        end if;
      end if;

      if (cnt_delay_l0 = trg_delay) then
        if (l0_delayed = '1') then
          l0_out <= '1';
        else
          l0_out <= '0';
        end if;
      end if;

      if (cnt_delay_l1 = trg_delay) then
        if (l1_delayed = '1') then
          l1_out <= '1';
        else
          l1_out <= '0';
        end if;
      end if;

      if (pt_in = '1') then
        cnt_after_ptrg <= (others => '0');
      end if;

    end if;
  end process;

end;