-- simple desiraliser (sfr)  1 to 4

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
--library UNISIM;
--use UNISIM.vcomponents.all;

entity cbbr_iserdes is
  port (
    clk40   : in  std_logic;
    reset_n : in  std_logic;
    di      : in  std_logic;
    dif     : in  std_logic;    
    enable  : in  std_logic;
    dout    : out std_logic_vector(3 downto 0));

end cbbr_iserdes;

architecture behv of cbbr_iserdes is
signal sfr : std_logic_vector(3 downto 0);
begin  -- behv

  ishift: process (clk40, reset_n)
  begin  -- process ishift
    if reset_n = '0' then               -- asynchronous reset (active low)
      sfr <= "0000";
    elsif clk40'event and clk40 = '1' then  -- rising clock edge
      if enable = '1' then
        sfr(3 downto 2) <= sfr(1 downto 0);  -- shift left
        sfr(1 downto 0) <= dif & di; 
      end if;
    end if;
  end process ishift;

  dout <= sfr;
end behv;