library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity timing_analyzer is
  port (
    clk40    : in std_logic;
    rst40    : in std_logic;

    clk_scsn   : in std_logic;
    rst_scsn   : in std_logic;

    signals  : in std_logic_vector(30 downto 0);
    trg_mask : in std_logic_vector(30 downto 0);
    trg_val  : in std_logic_vector(30 downto 0);
    arm      : in std_logic;
    post_cnt : in std_logic_vector(8 downto 0);
    status   : out std_logic_vector(7 downto 0);

    scsn_addr : in std_logic_vector(15 downto 0);
    scsn_data : out std_logic_vector(31 downto 0);
    scsn_req  : in std_logic;
    scsn_ack  : out std_logic
  );

end timing_analyzer;

architecture behav of timing_analyzer is

component dp_sram_512x32 is
generic (piper    : boolean  := false); -- pipelined read
port(
    wclk    : in  std_logic;
    rclk    : in  std_logic;
    we      : in  std_logic;
    waddr   : in  std_logic_vector( 8 downto 0);
    raddr   : in  std_logic_vector( 8 downto 0);
    din     : in  std_logic_vector(31 downto 0);
    dout    : out std_logic_vector(31 downto 0) );
end component;

  signal trg  : std_logic;
  signal trgd : std_logic;
  signal arm_r : std_logic;

  signal run  : std_logic;

  signal signals_r : std_logic_vector(31 downto 0);
  signal addr_counter : std_logic_vector(8 downto 0);
  signal cnt_posttrg : std_logic_vector(8 downto 0);
  signal we : std_logic;

  signal scsn_req_r : std_logic;

  signal ram_addr : std_logic_vector(8 downto 0);

begin

  trg <= '1' when (((signals xor trg_val) and trg_mask) = x"0000000" & "000") else '0';

  status <= cnt_posttrg(3 downto 0) & trg & trgd & arm_r & run;

  process (clk40, rst40)
  begin
    if rst40 = '1' then
      addr_counter <= (others => '0');
      signals_r <= (others => '0');
      ram_addr <= (others => '0');
      trgd <= '0';
      arm_r <= '0';
      run <= '0';
      we <= '0';
      scsn_req_r <= '0';
      scsn_ack   <= '0';
      cnt_posttrg <= (others => '1');
    elsif rising_edge(clk40) then
      signals_r <= trg & signals;
      arm_r     <= arm;

      -- clear trgd on rising edge of arm signal
      if (arm = '1' and arm_r = '0') then
        run  <= '1';
        trgd <= '0';
        cnt_posttrg  <= (others => '1');
      end if;

      if trg = '1' then
        trgd <= '1';
      end if;

      if cnt_posttrg /= "000000000" then
        if cnt_posttrg > post_cnt then
          cnt_posttrg <= cnt_posttrg - '1';
        elsif trgd = '1' then
          cnt_posttrg <= cnt_posttrg - '1';
        end if;
      end if;

      if run = '1' and cnt_posttrg = "000000000" then
        run <= '0';
      end if;

      scsn_req_r <= scsn_req;
      scsn_ack   <= scsn_req_r;

      if (run = '1') then
        addr_counter <= addr_counter + 1;
        ram_addr <= scsn_addr(ram_addr'range);
        we <= '1';
      else
        ram_addr <= scsn_addr(ram_addr'range) + addr_counter;
        we <= '0';
      end if;
    end if;
  end process;

bram_inst : dp_sram_512x32
generic map(piper => false)
port map(
    rclk    => clk40,
    wclk    => clk40,
    we      => we,
    waddr   => addr_counter,
    raddr   => ram_addr,
    din     => signals_r,
    dout    => scsn_data);

end;