library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity ttcex_out is
  port (
    clk           : in  std_logic;
    rst           : in  std_logic;

    a_channel     : in  std_logic;
    b_channel     : in  std_logic;

    a_channel_out : out std_logic;
    b_channel_out : out std_logic;

    ctrl          : in std_logic_vector(15 downto 0)
    );
end ttcex_out;

architecture behav of ttcex_out is
  begin

    process (clk)
      begin
        if rising_edge(clk) then
          if rst = '1' then
            a_channel_out <= '0';
            b_channel_out <= '1';
          else
            -- using '0' here is against spec but matches currently used
            -- configuration scripts
            if ctrl(0) = '0' then
              a_channel_out <= ctrl(1);
            else
              a_channel_out <= a_channel;
            end if;

            if ctrl(2) = '1' then
              b_channel_out <= ctrl(3);
            else
              b_channel_out <= b_channel;
            end if;
          end if;
        end if;
      end process;

  end;