library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

-- To Do : hamming protection of the memory

entity trg_lut is
  port (
    clk40  : in std_logic;
    rst40  : in std_logic;

    trg_ctb : in std_logic_vector(12 downto 0);
--    tlmu_in : in std_logic_vector(7 downto 0);
--    cbc_in  : in std_logic_vector(1 downto 0);
--    cba_in  : in std_logic_vector(1 downto 0);
--    bc_in   : in std_logic;

    pattern_tof : in std_logic_vector(7 downto 0);
    pattern_cba : in std_logic_vector(1 downto 0);
    pattern_cbc : in std_logic_vector(1 downto 0);
    pattern_match_tof : out std_logic;
    pattern_match_cba : out std_logic;
    pattern_match_cbc : out std_logic;

    lut_mon : out std_logic_vector(12 downto 0);

    trigger : out std_logic_vector(1 downto 0);

    scsn_addr : in std_logic_vector(15 downto 0);
    scsn_din  : in std_logic_vector(31 downto 0);
    scsn_we   : in std_logic;
    scsn_req  : in std_logic;
    scsn_dout : out std_logic_vector(31 downto 0);
    scsn_ack  : out std_logic
  );
end trg_lut;


architecture behav of trg_lut is

component lut_8k_2 is
generic (piperA : boolean  := false;  -- pipelined read
         piperB : boolean  := false); -- pipelined read
port(
    clkA  : in  std_logic;
    clkB  : in  std_logic;
    we    : in  std_logic;
    addrA : in  std_logic_vector( 8 downto 0);
    addrB : in  std_logic_vector(12 downto 0);
    dinA  : in  std_logic_vector(31 downto 0);
    doutA : out std_logic_vector(31 downto 0);
    doutB : out std_logic_vector( 1 downto 0) );
end component;

--component ram16k_w32_r2 is
--port(
--    clk     : in  std_logic;
--    we      : in  std_logic;
--    addrA   : in  std_logic_vector( 8 downto 0);
--    addrB   : in  std_logic_vector(12 downto 0);
--    dinA    : in  std_logic_vector(31 downto 0);
--    doutA   : out std_logic_vector(31 downto 0);
--    doutB   : out std_logic_vector( 1 downto 0) );
--end component;

  signal trigger_i : std_logic_vector(1 downto 0);

  signal lut_ra  : std_logic_vector(12 downto 0);
  type sm_type is (idle, clear);
  signal sm : sm_type;
  signal addr : std_logic_vector(8 downto 0);
  signal din  : std_logic_vector(scsn_din'range);
  signal we   : std_logic;
  signal req_clr    : std_logic;
  signal clr_addr   : std_logic_vector(addr'range);
  constant clr_addr_full  : std_logic_vector(clr_addr'range) := (others => '1');

begin

  --
  -- I/O mapping
  trigger <= trigger_i;

  process (clk40, rst40)
  begin
    if rst40 = '1' then
      lut_mon <= (others => '0');
    elsif rising_edge(clk40) then
      lut_mon <= lut_ra; -- bc_in & tlmu_in(7 downto 0) & cbc_in & cba_in;
    end if;
  end process;

  -- reading as LUT 8k x 2
  -- read/write scsn 512 x 32

--    lut_ra <= bc_in & tlmu_in & cbc_in & cba_in;
  lut_ra <= trg_ctb(8 downto 8) & trg_ctb(7 downto 0) & trg_ctb(10 downto 9) & trg_ctb(12 downto 11);

    process(clk40)
    begin
        if rising_edge(clk40) then
            if rst40='1' then
                req_clr <= '1';
                sm <= idle;
                clr_addr <= (others => '0');
            else

            if scsn_we='1' and scsn_addr(11 downto 9) = "111" then req_clr <= '1'; end if;

            case sm is
            when idle =>
                clr_addr <= (others => '0');
                if req_clr = '1' then sm <= clear; end if;
            when clear =>
                clr_addr <= clr_addr + 1;
                req_clr <= '0';
                if clr_addr = clr_addr_full then sm <= idle; end if;
            end case;
            end if;
        end if;
    end process;

    we   <= '1' when sm = clear else scsn_we when (scsn_addr(11 downto 9) = "000") else '0';
    din  <= (others => '0') when sm = clear else scsn_din;
    addr <= clr_addr when sm = clear else scsn_addr(addr'range);

bram_lut_inst: lut_8k_2
port map(
    clkA    => clk40,
    clkB    => clk40,
    we      => we,
    addrA   => addr,
    addrB   => lut_ra,
    dinA    => din,
    doutA   => scsn_dout,
    doutB   => trigger_i);

--bram_lut_inst : RAMB16_S2_S36
--  generic map (
--    WRITE_MODE_A => "READ_FIRST",
--    WRITE_MODE_B => "READ_FIRST"
--  )
--  port map (
--    -- port A : reading using BC
--    ADDRA( 1 downto 0) => cba_in,
--    ADDRA( 3 downto 2) => cbc_in,
--    ADDRA(11 downto 4) => tlmu_in,
--    ADDRA(12)  => bc_in,
--    DIA   => (others => '1'),
--    DOA   => trigger_i,
--    WEA   => '0',
--    ENA   => '1',
--    SSRA  => rst40,
--    CLKA  => clk40,
--
--    -- port B : read/write via SCSN
--    ADDRB => scsn_addr(8 downto 0),
--    DIB   => scsn_din,
--    DIPB  => (others => '1'),
--    DOB   => scsn_dout,
--    DOPB  => open,
--    WEB   => scsn_we,
--    ENB   => '1',
--    SSRB  => rst40,
--    CLKB  => clk40
--  );

  process (clk40, rst40)
  begin
    if rst40 = '1' then
      scsn_ack <= '0';
    elsif rising_edge(clk40) then
      if scsn_req = '1' then
        scsn_ack <= '1';
      else
        scsn_ack <= '0';
      end if;
    end if;
  end process;

--  cmp_pattern : process (clk40, rst40)
--  begin
--    if rst40 = '1' then
--      pattern_match_tof <= '0';
--      pattern_match_cba <= '0';
--      pattern_match_cbc <= '0';
--    elsif rising_edge(clk40) then
--      if cba_in = pattern_cba then
--        pattern_match_cba <= '1';
--      else
--        pattern_match_cba <= '0';
--      end if;
--
--      if cbc_in = pattern_cbc then
--        pattern_match_cbc <= '1';
--      else
--        pattern_match_cbc <= '0';
--      end if;
--
--      if tlmu_in = pattern_tof then
--        pattern_match_tof <= '1';
--      else
--        pattern_match_tof <= '0';
--      end if;
--    end if;
--  end process;

end;