library ieee, work; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.buildstamp.all; entity sys_config is generic ( trg_cnt_width : integer := 12 ); port( clk : in std_logic; rst : in std_logic; cbb_ctrl : out std_logic_vector( 1 downto 0); ttc_channel_ctrl : out std_logic_vector(15 downto 0); ptrg_to_l0_acc : out std_logic_vector(trg_cnt_width-1 downto 0); ptrg_to_l0_send : out std_logic_vector(trg_cnt_width-1 downto 0); ptrg_to_l1_acc : out std_logic_vector(trg_cnt_width-1 downto 0); ptrg_to_l1_send : out std_logic_vector(trg_cnt_width-1 downto 0); ptrg_to_idle : out std_logic_vector(trg_cnt_width-1 downto 0); ptrg_to_idle_nol0 : out std_logic_vector(trg_cnt_width-1 downto 0); ptrg_to_idle_nol1 : out std_logic_vector(trg_cnt_width-1 downto 0); ptrg_to_l0_delay : out std_logic_vector(trg_cnt_width-1 downto 0); a_channel_out_dis : out std_logic; gtu_busy_ctrl : out std_logic_vector(3 downto 0); pt_trg_mask : out std_logic_vector(15 downto 0); pt_trg_delays : out std_logic_vector(63 downto 0); cba_sampling : out std_logic_vector(1 downto 0); cbc_sampling : out std_logic_vector(1 downto 0); pattern_cba : out std_logic_vector(1 downto 0); pattern_cbc : out std_logic_vector(1 downto 0); pattern_tof : out std_logic_vector(7 downto 0); bc_offset : in std_logic_vector(11 downto 0); bc_l0 : in std_logic_vector(11 downto 0); bc_msg : in std_logic_vector(11 downto 0); bc_rst_val : out std_logic_vector(11 downto 0); tin1_opt_code : out std_logic_vector( 1 downto 0); tin2_opt_code : out std_logic_vector( 1 downto 0); tin3_opt_code : out std_logic_vector( 1 downto 0); tim_ana_trg_mask : out std_logic_vector(31 downto 0); tim_ana_trg_val : out std_logic_vector(31 downto 0); tim_ana_arm : out std_logic; tim_ana_postcnt : out std_logic_vector(8 downto 0); rnd_trg_thr : out std_logic_vector(31 downto 0); ram_cnt_clr : out std_logic; ram_cnt_capt : out std_logic; coinc_cnt_ctrl : out std_logic_vector(31 downto 0); ttcex_ctrl : out std_logic_vector(1 downto 0); ttcex_status : in std_logic_vector(9 downto 0); debug : in std_logic_vector(31 downto 0); scsn_addr : in std_logic_vector(15 downto 0); scsn_dout : in std_logic_vector(31 downto 0); scsn_din : out std_logic_vector(31 downto 0); scsn_req : in std_logic; scsn_ack : out std_logic; scsn_we : in std_logic; scsn_dout_com : out std_logic_vector(31 downto 0); scsn_addr_com : out std_logic_vector(15 downto 0); scsn_we_ta : out std_logic; scsn_req_ta : out std_logic; scsn_ack_ta : in std_logic; scsn_din_ta : in std_logic_vector(31 downto 0); scsn_addr_ta : out std_logic_vector(11 downto 0); scsn_we_ramcnt : out std_logic; scsn_req_ramcnt : out std_logic; scsn_ack_ramcnt : in std_logic; scsn_din_ramcnt : in std_logic_vector(31 downto 0); scsn_addr_ramcnt : out std_logic_vector(11 downto 0); scsn_we_lut : out std_logic; scsn_req_lut : out std_logic; scsn_ack_lut : in std_logic; scsn_din_lut : in std_logic_vector(31 downto 0); scsn_addr_lut : out std_logic_vector(11 downto 0); scsn_we_bctrg : out std_logic; scsn_req_bctrg : out std_logic; scsn_ack_bctrg : in std_logic; scsn_din_bctrg : in std_logic_vector(31 downto 0); scsn_addr_bctrg : out std_logic_vector(11 downto 0); scsn_we_tlrec : out std_logic; scsn_req_tlrec : out std_logic; scsn_ack_tlrec : in std_logic; scsn_din_tlrec : in std_logic_vector(31 downto 0); scsn_addr_tlrec : out std_logic_vector(11 downto 0) ); end sys_config; architecture arc of sys_config is signal syscfg_addr_r : std_logic_vector(11 downto 0); signal syscfg_wdata_r : std_logic_vector(31 downto 0); signal syscfg_rdata_i : std_logic_vector(31 downto 0); signal syscfg_req_r : std_logic; signal syscfg_we_r : std_logic; -- signal syscfg_ack_i : std_logic; signal scsn_dout_r : std_logic_vector(31 downto 0); signal scsn_addr_r : std_logic_vector(15 downto 0); signal scsn_we_r : std_logic; -- signal scsn_ack_r : std_logic; signal scsn_req_r : std_logic; signal scsn_we_ris : std_logic; signal cbb_ctrl_i : std_logic_vector( 1 downto 0); signal ttc_channel_ctrl_i : std_logic_vector(15 downto 0); signal pt_trg_mask_i : std_logic_vector(15 downto 0); type pt_trg_delay_array is array(1 downto 0) of std_logic_vector(31 downto 0); signal pt_trg_delays_i : pt_trg_delay_array; signal cba_sampling_i : std_logic_vector(1 downto 0); signal cbc_sampling_i : std_logic_vector(1 downto 0); signal pattern_cba_i : std_logic_vector(1 downto 0); signal pattern_cbc_i : std_logic_vector(1 downto 0); signal pattern_tof_i : std_logic_vector(7 downto 0); signal ptrg_to_l0_acc_i : std_logic_vector(trg_cnt_width-1 downto 0); signal ptrg_to_l0_send_i : std_logic_vector(trg_cnt_width-1 downto 0); signal ptrg_to_l1_acc_i : std_logic_vector(trg_cnt_width-1 downto 0); signal ptrg_to_l1_send_i : std_logic_vector(trg_cnt_width-1 downto 0); signal ptrg_to_idle_i : std_logic_vector(trg_cnt_width-1 downto 0); signal ptrg_to_idle_nol0_i : std_logic_vector(trg_cnt_width-1 downto 0); signal ptrg_to_idle_nol1_i : std_logic_vector(trg_cnt_width-1 downto 0); signal ptrg_to_l0_delay_i : std_logic_vector(trg_cnt_width-1 downto 0); signal a_channel_out_dis_i : std_logic; signal gtu_busy_ctrl_i : std_logic_vector(gtu_busy_ctrl'range); signal bc_rst_val_i : std_logic_vector(11 downto 0); signal tin1_opt_code_i : std_logic_vector(1 downto 0); signal tin2_opt_code_i : std_logic_vector(1 downto 0); signal tin3_opt_code_i : std_logic_vector(1 downto 0); signal tim_ana_trg_mask_i : std_logic_vector(31 downto 0); signal tim_ana_trg_val_i : std_logic_vector(31 downto 0); signal tim_ana_arm_i : std_logic; signal tim_ana_postcnt_i : std_logic_vector(8 downto 0); signal rnd_trg_thr_i : std_logic_vector(31 downto 0); signal ramcnt_clr_i : std_logic; signal ramcnt_capt_i : std_logic; signal ttcex_ctrl_i : std_logic_vector(1 downto 0); signal coinc_cnt_ctrl_i : std_logic_vector(31 downto 0); -- dummy values constant DATA_ZERO : std_logic_vector(31 downto 0) := x"01234567"; constant ADDR_ZERO : std_logic_vector(11 downto 0) := x"000"; -- address definitions -- -- general constant ADDR_CBB_CTRL : std_logic_vector(11 downto 0) := x"001"; constant ADDR_BUILD_INFO0 : std_logic_vector(11 downto 0) := x"002"; constant ADDR_BUILD_INFO1 : std_logic_vector(11 downto 0) := x"003"; -- trigger generation timings constant ADDR_PT_L0_ACC : std_logic_vector(11 downto 0) := x"010"; constant ADDR_PT_L0_SEND : std_logic_vector(11 downto 0) := x"011"; constant ADDR_PT_L1_ACC : std_logic_vector(11 downto 0) := x"012"; constant ADDR_PT_L1_SEND : std_logic_vector(11 downto 0) := x"013"; constant ADDR_PT_IDLE_NOL0 : std_logic_vector(11 downto 0) := x"014"; constant ADDR_PT_IDLE_NOL1 : std_logic_vector(11 downto 0) := x"015"; constant ADDR_PT_IDLE : std_logic_vector(11 downto 0) := x"016"; constant ADDR_PT_L0_DELAY : std_logic_vector(11 downto 0) := x"017"; -- trigger output constant ADDR_TTC_CHAN : std_logic_vector(11 downto 0) := x"020"; constant ADDR_A_CH_OUT_DIS : std_logic_vector(11 downto 0) := x"021"; constant ADDR_TIN1_OPT_CODE : std_logic_vector(11 downto 0) := x"022"; constant ADDR_TIN2_OPT_CODE : std_logic_vector(11 downto 0) := x"023"; constant ADDR_TIN3_OPT_CODE : std_logic_vector(11 downto 0) := x"024"; -- pretrigger inputs constant ADDR_CBA_SAMPLING : std_logic_vector(11 downto 0) := x"030"; constant ADDR_CBC_SAMPLING : std_logic_vector(11 downto 0) := x"031"; constant ADDR_PT_TRG_DLY1 : std_logic_vector(11 downto 0) := x"032"; constant ADDR_PT_TRG_DLY2 : std_logic_vector(11 downto 0) := x"033"; constant ADDR_GTU_BUSY_CTRL : std_logic_vector(11 downto 0) := x"034"; constant ADDR_RND_TRG_THR : std_logic_vector(11 downto 0) := x"040"; -- BC constant ADDR_BC_OFFSET : std_logic_vector(11 downto 0) := x"050"; constant ADDR_BC_L0 : std_logic_vector(11 downto 0) := x"051"; constant ADDR_BC_MSG : std_logic_vector(11 downto 0) := x"052"; constant ADDR_BC_RST_VAL : std_logic_vector(11 downto 0) := x"053"; -- pretrigger calculation constant ADDR_PT_TRG_MASK : std_logic_vector(11 downto 0) := x"060"; constant ADDR_PATTERN_CBA : std_logic_vector(11 downto 0) := x"061"; constant ADDR_PATTERN_CBC : std_logic_vector(11 downto 0) := x"062"; constant ADDR_PATTERN_TOF : std_logic_vector(11 downto 0) := x"063"; -- trigger counters (debugging) constant ADDR_COINC_CNT_CTRL: std_logic_vector(11 downto 0) := x"078"; -- timing analyzer control (to be moved) constant ADDR_TANA_TRGMASK : std_logic_vector(11 downto 0) := x"080"; constant ADDR_TANA_ARM : std_logic_vector(11 downto 0) := x"081"; constant ADDR_TANA_POSTCNT : std_logic_vector(11 downto 0) := x"082"; constant ADDR_TANA_TRGVAL : std_logic_vector(11 downto 0) := x"083"; -- RAM counter control constant ADDR_RAMCNT_CLR : std_logic_vector(11 downto 0) := x"090"; constant ADDR_RAMCNT_CAPT : std_logic_vector(11 downto 0) := x"091"; -- TTCex control constant ADDR_TTCEX_CTRL : std_logic_vector(11 downto 0) := x"0a0"; constant ADDR_TTCEX_STATUS : std_logic_vector(11 downto 0) := x"0a1"; -- debug information constant ADDR_DEBUG : std_logic_vector(11 downto 0) := x"0b0"; begin -- mapping of internal signals cbb_ctrl <= cbb_ctrl_i; ttc_channel_ctrl <= ttc_channel_ctrl_i; ptrg_to_l0_acc <= ptrg_to_l0_acc_i; ptrg_to_l0_send <= ptrg_to_l0_send_i; ptrg_to_l1_acc <= ptrg_to_l1_acc_i; ptrg_to_l1_send <= ptrg_to_l1_send_i; ptrg_to_idle <= ptrg_to_idle_i; ptrg_to_idle_nol0 <= ptrg_to_idle_nol0_i; ptrg_to_idle_nol1 <= ptrg_to_idle_nol1_i; ptrg_to_l0_delay <= ptrg_to_l0_delay_i; a_channel_out_dis <= a_channel_out_dis_i; gtu_busy_ctrl <= gtu_busy_ctrl_i; pt_trg_mask <= pt_trg_mask_i; pt_trg_delays <= pt_trg_delays_i(1) & pt_trg_delays_i(0); cba_sampling <= cba_sampling_i; cbc_sampling <= cbc_sampling_i; pattern_cba <= pattern_cba_i; pattern_cbc <= pattern_cbc_i; pattern_tof <= pattern_tof_i; bc_rst_val <= bc_rst_val_i; tin1_opt_code <= tin1_opt_code_i; tin2_opt_code <= tin2_opt_code_i; tin3_opt_code <= tin3_opt_code_i; tim_ana_trg_mask <= tim_ana_trg_mask_i; tim_ana_trg_val <= tim_ana_trg_val_i; tim_ana_arm <= tim_ana_arm_i; tim_ana_postcnt <= tim_ana_postcnt_i; rnd_trg_thr <= rnd_trg_thr_i; ram_cnt_clr <= ramcnt_clr_i; ram_cnt_capt <= ramcnt_capt_i; ttcex_ctrl <= ttcex_ctrl_i; coinc_cnt_ctrl <= coinc_cnt_ctrl_i; scsn_addr_ta <= scsn_addr_r(11 downto 0); scsn_addr_ramcnt <= scsn_addr_r(11 downto 0); scsn_addr_lut <= scsn_addr_r(11 downto 0); scsn_addr_bctrg <= scsn_addr_r(11 downto 0); scsn_addr_tlrec <= scsn_addr_r(11 downto 0); -- -- SCSN handling scsn_we_ris <= scsn_we and not scsn_we_r; process (clk, rst) begin if rst = '1' then syscfg_wdata_r <= (others => '0'); elsif rising_edge(clk) then syscfg_wdata_r <= scsn_dout_r; end if; end process; process (clk) variable msb_addr : std_logic_vector(3 downto 0); begin if rising_edge(clk) then -- Register stages scsn_dout_r <= scsn_dout; scsn_addr_r <= scsn_addr; scsn_we_r <= scsn_we; scsn_req_r <= scsn_req; scsn_dout_com <= scsn_dout; scsn_addr_com <= scsn_addr; syscfg_addr_r <= scsn_addr_r(syscfg_addr_r'range); -- Initialization scsn_we_ramcnt <= '0'; scsn_we_lut <= '0'; scsn_we_ta <= '0'; scsn_we_bctrg <= '0'; scsn_req_ramcnt <= '0'; scsn_req_lut <= '0'; scsn_req_ta <= '0'; scsn_req_bctrg <= '0'; msb_addr := scsn_addr(15 downto 12); case msb_addr is -- SCSN address ranges when x"1" => scsn_din <= scsn_din_ta; scsn_ack <= scsn_ack_ta; scsn_req_ta <= scsn_req; scsn_we_ta <= scsn_we_ris; when x"2" => scsn_din <= scsn_din_ramcnt; scsn_ack <= scsn_ack_ramcnt; scsn_req_ramcnt <= scsn_req; scsn_we_ramcnt <= scsn_we_ris; when x"3" => scsn_din <= scsn_din_lut; scsn_ack <= scsn_ack_lut; scsn_req_lut <= scsn_req; scsn_we_lut <= scsn_we_ris; when x"4" => scsn_din <= scsn_din_bctrg; scsn_ack <= scsn_ack_bctrg; scsn_req_bctrg <= scsn_req; scsn_we_bctrg <= scsn_we_ris; when x"5" => scsn_din <= scsn_din_tlrec; scsn_ack <= scsn_ack_tlrec; scsn_req_tlrec <= scsn_req; scsn_we_tlrec <= scsn_we_ris; when x"0" => scsn_din <= syscfg_rdata_i; scsn_ack <= syscfg_req_r; -- generate ack from req (1 clock -- after request) syscfg_we_r <= scsn_we_ris; syscfg_req_r <= scsn_req_r; when x"6" | x"7" => NULL; when others => scsn_din <= (others => 'X'); end case; end if; end process; -- -- system configuration read with syscfg_addr_r(11 downto 0) select syscfg_rdata_i <= DATA_ZERO when ADDR_ZERO, x"0000000" & "00" & cbb_ctrl_i when ADDR_CBB_CTRL, "0000000" & build_clean & build_date(23 downto 0) when ADDR_BUILD_INFO0, build_time & build_rev when ADDR_BUILD_INFO1, x"0000" & ttc_channel_ctrl_i when ADDR_TTC_CHAN, x"00000" & ptrg_to_l0_acc_i when ADDR_PT_L0_ACC, x"00000" & ptrg_to_l0_send_i when ADDR_PT_L0_SEND, x"00000" & ptrg_to_l1_acc_i when ADDR_PT_L1_ACC, x"00000" & ptrg_to_l1_send_i when ADDR_PT_L1_SEND, x"00000" & ptrg_to_idle_i when ADDR_PT_IDLE, x"00000" & ptrg_to_idle_nol0_i when ADDR_PT_IDLE_NOL0, x"00000" & ptrg_to_idle_nol1_i when ADDR_PT_IDLE_NOL1, x"00000" & ptrg_to_l0_delay_i when ADDR_PT_L0_DELAY, x"0000000" & "000" & a_channel_out_dis_i when ADDR_A_CH_OUT_DIS, x"0000000" & gtu_busy_ctrl_i when ADDR_GTU_BUSY_CTRL, x"0000" & pt_trg_mask_i when ADDR_PT_TRG_MASK, pt_trg_delays_i(0) when ADDR_PT_TRG_DLY1, pt_trg_delays_i(1) when ADDR_PT_TRG_DLY2, x"0000000" & "00" & cba_sampling_i when ADDR_CBA_SAMPLING, x"0000000" & "00" & cbc_sampling_i when ADDR_CBC_SAMPLING, x"0000000" & "00" & pattern_cba_i when ADDR_PATTERN_CBA, x"0000000" & "00" & pattern_cbc_i when ADDR_PATTERN_CBC, x"000000" & pattern_tof_i when ADDR_PATTERN_TOF, coinc_cnt_ctrl_i when ADDR_COINC_CNT_CTRL, x"00000" & bc_offset when ADDR_BC_OFFSET, x"00000" & bc_l0 when ADDR_BC_L0, x"00000" & bc_msg when ADDR_BC_MSG, x"00000" & bc_rst_val_i when ADDR_BC_RST_VAL, x"0000000" & "00" & tin1_opt_code_i when ADDR_TIN1_OPT_CODE, x"0000000" & "00" & tin2_opt_code_i when ADDR_TIN2_OPT_CODE, x"0000000" & "00" & tin3_opt_code_i when ADDR_TIN3_OPT_CODE, tim_ana_trg_mask_i when ADDR_TANA_TRGMASK, tim_ana_trg_val_i when ADDR_TANA_TRGVAL, x"0000000" & "000" & tim_ana_arm_i when ADDR_TANA_ARM, x"00000" & "000" & tim_ana_postcnt_i when ADDR_TANA_POSTCNT, rnd_trg_thr_i when ADDR_RND_TRG_THR, x"0000000" & "000" & ramcnt_clr_i when ADDR_RAMCNT_CLR, x"0000000" & "000" & ramcnt_capt_i when ADDR_RAMCNT_CAPT, x"0000000" & "00" & ttcex_ctrl_i when ADDR_TTCEX_CTRL, x"00000" & "00" & ttcex_status when ADDR_TTCEX_STATUS, debug when ADDR_DEBUG, x"deadbeaf" when others; -- -- system configuration write process(clk) begin if rising_edge(clk) then if rst = '1' then cbb_ctrl_i <= (others => '0'); ptrg_to_l0_acc_i <= conv_std_logic_vector( 43, ptrg_to_l0_acc_i'length); ptrg_to_l0_send_i <= conv_std_logic_vector( 47, ptrg_to_l0_send_i'length); ptrg_to_l1_acc_i <= conv_std_logic_vector(250, ptrg_to_l1_acc_i'length); ptrg_to_l1_send_i <= conv_std_logic_vector(311, ptrg_to_l1_send_i'length); ptrg_to_idle_i <= conv_std_logic_vector(500, ptrg_to_idle_i'length); ptrg_to_idle_nol0_i <= conv_std_logic_vector(200, ptrg_to_idle_nol0_i'length); ptrg_to_idle_nol1_i <= conv_std_logic_vector(350, ptrg_to_idle_nol1_i'length); ptrg_to_l0_delay_i <= conv_std_logic_vector(46, ptrg_to_idle_i'length); ttc_channel_ctrl_i <= (others => '0'); a_channel_out_dis_i <= '0'; tin1_opt_code_i <= (others => '0'); tin2_opt_code_i <= (others => '0'); tin3_opt_code_i <= (others => '0'); cba_sampling_i <= (others => '0'); cbc_sampling_i <= (others => '0'); pt_trg_delays_i <= (others => (others => '0')); gtu_busy_ctrl_i <= (others => '0'); rnd_trg_thr_i <= (others => '0'); bc_rst_val_i <= conv_std_logic_vector(225, bc_rst_val_i'length); pt_trg_mask_i <= (others => '0'); pattern_cba_i <= (others => '0'); pattern_cbc_i <= (others => '0'); pattern_tof_i <= (others => '0'); tim_ana_trg_mask_i <= (others => '0'); tim_ana_trg_val_i <= (others => '1'); tim_ana_arm_i <= '0'; tim_ana_postcnt_i <= conv_std_logic_vector(100, tim_ana_postcnt_i'length); coinc_cnt_ctrl_i <= (others => '0'); ramcnt_capt_i <= '1'; ramcnt_clr_i <= '0'; else if syscfg_we_r = '1' then case syscfg_addr_r(11 downto 0) is when ADDR_CBB_CTRL => cbb_ctrl_i <= syscfg_wdata_r(cbb_ctrl_i'range); when ADDR_TTC_CHAN => ttc_channel_ctrl_i <= syscfg_wdata_r(15 downto 0); when ADDR_PT_L0_ACC => ptrg_to_l0_acc_i <= syscfg_wdata_r(trg_cnt_width-1 downto 0); when ADDR_PT_L0_SEND => ptrg_to_l0_send_i <= syscfg_wdata_r(trg_cnt_width-1 downto 0); when ADDR_PT_L1_ACC => ptrg_to_l1_acc_i <= syscfg_wdata_r(trg_cnt_width-1 downto 0); when ADDR_PT_L1_SEND => ptrg_to_l1_send_i <= syscfg_wdata_r(trg_cnt_width-1 downto 0); when ADDR_PT_IDLE => ptrg_to_idle_i <= syscfg_wdata_r(trg_cnt_width-1 downto 0); when ADDR_PT_IDLE_NOL0 => ptrg_to_idle_nol0_i <= syscfg_wdata_r(trg_cnt_width-1 downto 0); when ADDR_PT_IDLE_NOL1 => ptrg_to_idle_nol1_i <= syscfg_wdata_r(trg_cnt_width-1 downto 0); when ADDR_PT_L0_DELAY => ptrg_to_l0_delay_i <= syscfg_wdata_r(trg_cnt_width-1 downto 0); when ADDR_A_CH_OUT_DIS => a_channel_out_dis_i <= syscfg_wdata_r(0); when ADDR_GTU_BUSY_CTRL => gtu_busy_ctrl_i <= syscfg_wdata_r(gtu_busy_ctrl_i'range); when ADDR_PT_TRG_MASK => pt_trg_mask_i <= syscfg_wdata_r(15 downto 0); when ADDR_PT_TRG_DLY1 => pt_trg_delays_i(0) <= syscfg_wdata_r; when ADDR_PT_TRG_DLY2 => pt_trg_delays_i(1) <= syscfg_wdata_r; when ADDR_CBA_SAMPLING => cba_sampling_i <= syscfg_wdata_r(1 downto 0); when ADDR_CBC_SAMPLING => cbc_sampling_i <= syscfg_wdata_r(1 downto 0); when ADDR_PATTERN_CBA => pattern_cba_i <= syscfg_wdata_r(1 downto 0); when ADDR_PATTERN_CBC => pattern_cbc_i <= syscfg_wdata_r(1 downto 0); when ADDR_PATTERN_TOF => pattern_tof_i <= syscfg_wdata_r(pattern_tof_i'range); when ADDR_BC_RST_VAL => bc_rst_val_i <= syscfg_wdata_r(11 downto 0); when ADDR_TIN1_OPT_CODE => tin1_opt_code_i <= syscfg_wdata_r(1 downto 0); when ADDR_TIN2_OPT_CODE => tin2_opt_code_i <= syscfg_wdata_r(1 downto 0); when ADDR_TIN3_OPT_CODE => tin3_opt_code_i <= syscfg_wdata_r(1 downto 0); when ADDR_TANA_TRGMASK => tim_ana_trg_mask_i <= syscfg_wdata_r; when ADDR_TANA_TRGVAL => tim_ana_trg_val_i <= syscfg_wdata_r; when ADDR_TANA_ARM => tim_ana_arm_i <= syscfg_wdata_r(0); when ADDR_TANA_POSTCNT => tim_ana_postcnt_i <= syscfg_wdata_r(8 downto 0); when ADDR_RND_TRG_THR => rnd_trg_thr_i <= syscfg_wdata_r; when ADDR_RAMCNT_CLR => ramcnt_clr_i <= syscfg_wdata_r(0); when ADDR_RAMCNT_CAPT => ramcnt_capt_i <= syscfg_wdata_r(0); when ADDR_TTCEX_CTRL => ttcex_ctrl_i <= syscfg_wdata_r(1 downto 0); when ADDR_COINC_CNT_CTRL => coinc_cnt_ctrl_i <= syscfg_wdata_r; when others => null; end case; end if; end if; end if; end process; end arc;