library ieee;
use ieee.std_logic_1164.all;

entity shiftreg_piso is
  generic (
    width : natural := 22
  );
  port (
    clk40 : in std_logic;
    rst40 : in std_logic;

    din : in std_logic_vector(width-1 downto 0);
    pload : in std_logic;

    sin : in std_logic;
    sout : out std_logic;
    shift : in std_logic
  );
end shiftreg_piso;

architecture behav of shiftreg_piso is

  signal q : std_logic_vector(width-1 downto 0);

begin
  process (clk40)
  begin
    if rising_edge(clk40) then
      if rst40 = '1' then
        q <= (others => '0');
      else
        if pload = '1' then
          q <= din;
        elsif shift = '1' then
          q <= q(width-2 downto 0) & sin;
        end if;
      end if;
    end if;
  end process;

  sout <= q(width-1);

end;