library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity random_pulser is
  port (
    clk40 : in std_logic;
    rst40 : in std_logic;

    thr : in std_logic_vector(31 downto 0);

    pulse : out std_logic
  );
end random_pulser;

architecture behav of random_pulser is

component psrg is
generic (N : Natural := 32);
port (
    clk   : in  std_logic;
    rst   : in  std_logic;
    q     : out std_logic_vector(N-1 downto 0));
end component;


  signal rnd : std_logic_vector(31 downto 0);

--  signal rnd_valid : std_logic;
  signal kn : Integer range 0 to 1023;

begin

--rng : entity work.mersenne_twister
--  port map (
--    clk40 => clk40,
--    rst40 => rst40,
--    rnd   => rnd,
--    valid => rnd_valid
--  );

  rng: psrg
    generic map(N => rnd'length)
    port map(
      clk   => clk40,
      rst   => rst40,
      q     => rnd);

  process (clk40)
  begin
    if rising_edge(clk40) then
      if rst40 = '1' then
        pulse <= '0';
        kn <= 0;
      else
        if (kn >= 20) then
          if (rnd <= thr) then
            pulse <= '1';
          else
            pulse <= '0';
          end if;
        end if;
      end if;

      if kn = 623 then kn <= 4;
                  else kn <= kn + 1; end if;

    end if;
  end process;

end;