LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

ENTITY ram_cnt_ref IS
generic(Na : Positive := 7);
port(
    clk     : in    std_logic;
    rst     : in    std_logic;
    inputs  : in    std_logic_vector(2**Na-1 downto 0);
    inp_msk : in    std_logic_vector(2**Na-1 downto 0);
    track   : in    std_logic;
    ack     : in    std_logic;
    raddr   : in    std_logic_vector(15 downto 0);
    rdata   : out   std_logic_vector(31 downto 0));
END ram_cnt_ref;

ARCHITECTURE sim OF ram_cnt_ref IS

type counter_arr is array(0 to inputs'high) of Natural;

signal my_counter      : counter_arr;
signal my_counter_cap  : counter_arr;

signal ra : Natural range 0 to 2**Na-1;
signal rundata1 : Natural;
signal rundata2 : Natural;
signal rundata3 : Natural;

begin
    process(clk)
    begin
        if rising_edge(clk) then
            for i in 0 to inputs'high loop
                if rst='1' then my_counter(i) <= 0;
                elsif inputs(i)='1' and inp_msk(i)='1' then
                    my_counter(i) <= my_counter(i) + 1;
                    if track='1' then
                        my_counter_cap(i) <= my_counter(i) + 1;
                    end if;
                elsif track='1' then my_counter_cap(i) <= my_counter(i);
                end if;
            end loop;
            if ack='0' then
                rundata1 <= my_counter(ra);
                rundata2 <= rundata1;
                rundata3 <= rundata2;
            end if;
        end if;
    end process;

    ra <= conv_integer(raddr(Na-1 downto 0)); -- read address

    with raddr(11 downto 10) select
    rdata <= (others => '0')    when "01" | "11", -- upper part, here the implementation is 31 bit only
             conv_std_logic_vector(rundata3, rdata'length) when "00",
             conv_std_logic_vector(my_counter_cap(ra), rdata'length) when "10",
             (others => 'X')    when others;

end;