LIBRARY ieee;
use ieee.std_logic_1164.all;

use std.textio.all;
use IEEE.std_logic_textio.all;

ENTITY ram_cnt_log IS
generic(Na : Positive := 7;
        logfile : string := "./DATA/compare.log");
port(
    clk     : in    std_logic;
    ack     : in    std_logic;
    capture : in    std_logic;
    raddr   : in    std_logic_vector(15 downto 0);
    rdata_s : in    std_logic_vector(31 downto 0);
    rdata_r : in    std_logic_vector(31 downto 0));
END ram_cnt_log;

ARCHITECTURE sim OF ram_cnt_log IS

file outfile_wr : TEXT open write_mode is logfile;

signal errors : Natural;

begin
    process
    variable outline : line;
    variable read_num : Natural := 0;
    begin
        wait until falling_edge(capture);
        read_num := read_num + 1;
        write(outline, string'("# fallling edge of capture detected, start checking..."));
        writeline(outfile_wr, outline);
        write(outline, string'("# reading No."));
        write(outline, read_num);
        writeline(outfile_wr, outline);
    end process;

    process
    variable outline : line;
    variable errors_new : Natural;
    begin
        wait until rising_edge(ack);
        wait until falling_edge(clk);
        write(outline, now);
        write(outline, string'(" 0x"));
        hwrite(outline, raddr);
        write(outline, string'(" 0x"));
        hwrite(outline, rdata_s);
        write(outline, string'(" 0x"));
        hwrite(outline, rdata_r);
        write(outline, string'(" err "));
        errors_new := errors;
        if rdata_s /= rdata_r then
            errors <= errors + 1;
            errors_new := errors + 1;
        end if;
        write(outline, errors_new);
        if raddr(11)='1' then write(outline, string'(" cap "));
                         else write(outline, string'(" run "));
        end if;
        writeline(outfile_wr, outline);
    end process;
end;