library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity ram_cnt_cnt is generic(N : Positive := 7); port( clk : in std_logic; srst : in std_logic; selected : in std_logic; cnt_ena : in std_logic; track : in std_logic; q_curr : out std_logic_vector(N-1 downto 0); cout : out std_logic; q_hold : out std_logic_vector(N-1 downto 0); cout_hold : out std_logic); end ram_cnt_cnt; architecture behav of ram_cnt_cnt is signal q_curr_i : std_logic_vector(N-1 downto 0); signal q_next : std_logic_vector(N-1 downto 0); signal almost_f : std_logic; signal cout_i : std_logic; signal cout_next : std_logic; constant cnt_max : std_logic_vector(N-1 downto 0) := (others => '1'); --constant cnt_maxM1 : std_logic_vector(N-1 downto 0) := (0 => '0', others => '1'); begin process(clk) begin if rising_edge(clk) then cout_i <= cout_next; q_curr_i <= q_next; if track = '1' then q_hold <= q_next; cout_hold <= cout_next; end if; end if; end process; q_curr <= q_curr_i; cout <= cout_i; almost_f <= '1' when q_curr_i = cnt_max else '0'; process(almost_f, cout_i, q_curr_i, selected, cnt_ena, srst) variable case_var : std_logic_vector(3 downto 0); begin if srst = '1' then cout_next <= '0'; q_next <= (others => '0'); else case_var := cnt_ena & selected & almost_f & cout_i; q_next <= q_curr_i; cout_next <= cout_i; case case_var is when "0000" | "0001" | "0010" | "0011" | "0100" | "0110" => NULL; when "1011" => NULL; -- should not happen!!! when "0101" | "0111" => cout_next <= '0'; when "1001" | "1100" => q_next <= q_curr_i + 1; when "1000" | "1010" | "1110" => q_next <= q_curr_i + 1; cout_next <= almost_f; when "1101" => q_next <= q_curr_i + 1; cout_next <= '0'; when "1111" => q_next <= (others => '0'); cout_next <= '1'; when others => q_next <= (others => '-'); cout_next <= '-'; end case; end if; end process; end;