LIBRARY ieee;
use ieee.std_logic_1164.all;

ENTITY ram_cnt_checker IS
generic(Na : Positive := 7;
        logfile : string := "./compare.log");
port(
    clk     : in    std_logic;
    rst     : in    std_logic;

    inputs  : in    std_logic_vector(2**Na-1 downto 0);
    inp_msk : in    std_logic_vector(2**Na-1 downto 0);
    track   : in    std_logic;
    clear   : in    std_logic;

    ack     : in    std_logic;
    raddr   : in    std_logic_vector(15 downto 0);
    rdata_s : in    std_logic_vector(31 downto 0));
END ram_cnt_checker;

architecture struct of ram_cnt_checker is

component ram_cnt_ref IS
generic(Na : Positive := 7);
port(
    clk     : in    std_logic;
    rst     : in    std_logic;
    inputs  : in    std_logic_vector(2**Na-1 downto 0);
    inp_msk : in    std_logic_vector(2**Na-1 downto 0);
    track   : in    std_logic;
    ack     : in    std_logic;
    raddr   : in    std_logic_vector(15 downto 0);
    rdata   : out   std_logic_vector(31 downto 0));
END component;

component ram_cnt_log IS
generic(Na : Positive := 7;
        logfile : string := "./DATA/compare.log");
port(
    clk     : in    std_logic;
    ack     : in    std_logic;
    capture : in    std_logic;
    raddr   : in    std_logic_vector(15 downto 0);
    rdata_s : in    std_logic_vector(31 downto 0);
    rdata_r : in    std_logic_vector(31 downto 0));
END component;

signal dout_exp : std_logic_vector(31 downto 0);
signal rst_clr  : std_logic;

begin
    rst_clr <= rst or clear;

rc_ref: ram_cnt_ref
generic map(Na => Na)
port map(
    clk     => clk,
    rst     => rst_clr,
    inputs  => inputs,
    inp_msk => inp_msk,
    track   => track,
    ack     => ack,
    raddr   => raddr,
    rdata   => dout_exp);

rc_log: ram_cnt_log
generic map(Na => Na,
        logfile => logfile)
port map(
    clk     => clk,
    ack     => ack,
    capture => track,
    raddr   => raddr,
    rdata_s => rdata_s,
    rdata_r => dout_exp);

end;