library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity pt_align is
  generic (
    no_inputs : integer := 15;
    no_delays : integer := 8
  );
  port (
      clk             : in  std_logic;
      rst             : in  std_logic;

      trg_src         : in  std_logic_vector(15 downto 0);
      trg_ctb         : out std_logic_vector(15 downto 0);
      trg_ctb_r       : out std_logic_vector(15 downto 0);

      trg_req         : out std_logic;
      trg_req_r       : out std_logic;

      trg_delays      : in  std_logic_vector(63 downto 0);
      trg_mask        : in  std_logic_vector(15 downto 0)
  );
end pt_align;

architecture behav of pt_align is

  type trg_array is array(15 downto 0) of std_logic_vector(no_delays-1 downto 0);
  signal trg_aligned  : trg_array;
  type trg_delays_array is array(15 downto 0) of std_logic_vector(3 downto 0);
  signal trg_delay    : trg_delays_array;

  signal trg_ctb_i    : std_logic_vector(15 downto 0);
  signal trg_ctb_r_i  : std_logic_vector(15 downto 0);

  signal trg_req_i    : std_logic;
  signal trg_req_r_i  : std_logic;

begin

  trg_ctb        <= trg_ctb_i;
  trg_ctb_r      <= trg_ctb_r_i;
  trg_req        <= trg_req_i;
  trg_req_r      <= trg_req_r_i;

  delay_gen : for i in 0 to 15 generate
    trg_delay(i) <= trg_delays(4*i+3 downto 4*i);

    process (clk)
    begin
      if rising_edge(clk) then
        if rst = '1' then
          trg_aligned(i) <= (others => '0');
        else
          trg_aligned(i)(0) <= trg_src(i);
          delay_shift : for ii in 1 to 7 loop
            trg_aligned(i)(ii) <= trg_aligned(i)(ii-1);
          end loop;
        end if;
      end if;
    end process;
  end generate;

  pt_delay_mux : for i in 0 to 15 generate
    with trg_delay(i) select
      trg_ctb_i(i) <= trg_src(i)                             when x"0",
                      trg_aligned(i)(0)                      when x"1",
                      trg_aligned(i)(1)                      when x"2",
                      trg_aligned(i)(2)                      when x"3",
                      trg_aligned(i)(3)                      when x"4",
                      trg_aligned(i)(4)                      when x"5",
                      trg_aligned(i)(5)                      when x"6",
                      trg_aligned(i)(6)                      when x"7",
                      trg_src(i)        or trg_aligned(i)(0) when x"8",
                      trg_aligned(i)(0) or trg_aligned(i)(1) when x"9",
                      trg_aligned(i)(1) or trg_aligned(i)(2) when x"a",
                      trg_aligned(i)(2) or trg_aligned(i)(3) when x"b",
                      trg_aligned(i)(3) or trg_aligned(i)(4) when x"c",
                      trg_aligned(i)(4) or trg_aligned(i)(5) when x"d",
                      trg_aligned(i)(5) or trg_aligned(i)(6) when x"e",
                      trg_aligned(i)(6) or trg_aligned(i)(7) when x"f",
                      trg_src(i) when others;
  end generate;

  -- check trigger condition
  trg_req_i <= '1' when ((trg_ctb_r_i(15 downto 2) & trg_ctb_i(1 downto 0)) and trg_mask) /= x"0000" else '0';

  process (clk)
    begin
      if rising_edge(clk) then
        trg_req_r_i <= trg_req_i;
        trg_ctb_r_i <= trg_ctb_i;
      end if;
    end process;

end;