library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;

 entity del_coinc_cnt_en is
   generic (
     depth           : integer := 6;
     ref_offset      : integer := 2
   );
   port (
     clk40     : in std_logic;
     rst40     : in std_logic;
     enable    : in std_logic;
     ref       : in std_logic;
     sig       : in std_logic;

     cnt_en    : out std_logic_vector(depth-1 downto 0)
   );
 end del_coinc_cnt_en;

 architecture behav of del_coinc_cnt_en is

   signal cnt_en_t : std_logic_vector(depth-1 downto 0);

   signal sig_d    : std_logic_vector(depth-1 downto 0);
   signal ref_d    : std_logic_vector(ref_offset-1 downto 0);

 begin

   -- counter enables
   gen_cnt_en : for i in 0 to depth-1 generate
     process (clk40, rst40)
     begin
       if rst40 = '1' then
         cnt_en_t(i) <= '0';
       elsif rising_edge(clk40) then
         if ref_d(ref_offset-1) = '1' and sig_d(i) = '1' and enable = '1' then
           cnt_en_t(i) <= '1' ;
         else
           cnt_en_t(i) <= '0';
         end if;
       end if;
     end process;

     cnt_en(i) <= cnt_en_t(i);

   end generate;

   -- delayed sig
   gen_sig_d : for i in 1 to depth-1 generate
     process (clk40, rst40)
     begin
       if rst40 = '1' then
         sig_d(i) <= '0';
       elsif rising_edge(clk40) then
           sig_d(i) <= sig_d(i-1);
       end if;
     end process;
   end generate;

   process (clk40, rst40)
   begin
     if rst40 = '1' then
       sig_d(0) <= '0';
     elsif rising_edge(clk40) then
       sig_d(0) <= sig;
     end if;
   end process;


   -- delayed reference
   gen_ref_d : for i in 1 to ref_offset-1 generate
     process (clk40, rst40)
     begin
       if rst40 = '1'  then
         ref_d(i) <= '0';
       elsif rising_edge(clk40) then
           ref_d(i) <= ref_d(i-1);
       end if;
     end process;
   end generate;

   process (clk40, rst40)
   begin
     if rst40 = '1' then
       ref_d(0) <= '0';
     elsif rising_edge(clk40) then
       ref_d(0) <= ref;
     end if;
   end process;


end;