library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library unisim;
--use unisim.vcomponents.all;

entity cb_ac_sample is

  port (
    clk40: in std_logic;
    rst40: in std_logic;
    clk80: in std_logic;
    rst80: in std_logic;

    cb_sample_par: in std_logic_vector(1 downto 0);
    cb_in: in std_logic_vector(1 downto 0);
    cb_out: out std_logic_vector(3 downto 0)
  );

end cb_ac_sample;

architecture oversample160 of cb_ac_sample is

  signal cb_par     : std_logic_vector(7 downto 0);
  signal cb_par_r : std_logic_vector(7 downto 0);

  begin

    process (clk80, rst80)
    begin
      if rst80 = '1' then
        cb_par <= (others => '0');
      elsif rising_edge(clk80) then
        cb_par(0) <= cb_in(0);
        cb_par(1) <= cb_in(1);
        cb_parallel : for i in 1 to 3 loop
          cb_par(2*i  ) <= cb_par(2*i-2);
          cb_par(2*i+1) <= cb_par(2*i-1);
        end loop;
      end if;
    end process;

  process (clk40, rst40)
  begin
    if rst40 = '1' then
      cb_par_r  <= (others => '0');
    elsif rising_edge(clk40) then
      cb_par_r <= cb_par;
    end if;
  end process;

  with cb_sample_par select
      cb_out <= cb_par_r(6 downto 3) when "00",
                cb_par_r(5 downto 2) when "01",
                cb_par_r(4 downto 1) when "10",
                cb_par_r(3 downto 0) when "11",
                cb_par_r(3 downto 0) when others;

  end oversample160;