library ieee;
use ieee.std_logic_1164.all;

entity busy is
  port (
    clk           : in  std_logic;
    rst           : in  std_logic;
    clk80         : in  std_logic;
    rst80         : in  std_logic;

    busy_gtu_ddr  : in  std_logic_vector(1 downto 0);
    ctrl          : in  std_logic_vector(3 downto 0);  -- control signal for busy
                                                       -- bit 1: 0: ignore
                                                       --        1: use GTU busy
                                                       -- bit 0: select edge

    busy_mon      : out std_logic;      -- busy for monitoring on tim. analyzer
    busy_out      : out std_logic       -- busy for trigger protection
  );
end busy;

architecture behav of busy is

signal idx         : std_logic;
signal busy_cap    : std_logic_vector(3 downto 0);
signal busy_i      : std_logic;

begin
  -- output mapping
  busy_mon <= busy_i;
  busy_out <= busy_i when ctrl(0) = '1' else '0';

  -- busy is oversampled with 80 MHz DDR
  -- synchronise to 40 MHz clock
  process (clk80,rst80)
  begin
    if rising_edge(clk80) then
      if rst80 = '1' then
        idx <= '0';
        busy_cap <= (others => '0');
      else
        idx <= not idx;
        if idx = '0' then
          busy_cap(1 downto 0) <= busy_gtu_ddr;
        else
          busy_cap(3 downto 2) <= busy_gtu_ddr;
        end if;
      end if;
    end if;
  end process;

  -- select which edge to use
  with ctrl(2 downto 1) select
    busy_i   <= busy_cap(0) when "00",
                busy_cap(1) when "01",
                busy_cap(2) when "10",
                busy_cap(3) when "11",
                '0' when others;

end;