library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity bc_cnt is
  port (
      clk         : in  std_logic;
      rst         : in  std_logic;

      bc_reset    : in  std_logic;
      l0          : in  std_logic;
      l2a         : in  std_logic;
      l2a_msg     : in  std_logic_vector(95 downto 0);

      bc          : out std_logic_vector(11 downto 0);
      bc_offset   : out std_logic_vector(11 downto 0);
      bc_l0       : out std_logic_vector(11 downto 0);
      bc_msg      : out std_logic_vector(11 downto 0);

      bc_rst_val  : in  std_logic_vector(11 downto 0);
      bc_max_val  : in  std_logic_vector(11 downto 0)
  );
end bc_cnt;

architecture behav of bc_cnt is

  signal bc_i     : std_logic_vector(11 downto 0);
  signal bc_l0_i  : std_logic_vector(11 downto 0);
  signal bc_msg_i : std_logic_vector(11 downto 0);

  begin

    -- output mapping
    bc      <= bc_i;
    bc_l0   <= bc_l0_i;
    bc_msg  <= bc_msg_i;

    process (clk)
      begin
        if rising_edge(clk) then
          if rst = '1' then
            bc_i         <= (others => '0');
            bc_offset    <= (others => '0');
            bc_l0_i      <= (others => '0');
            bc_msg_i     <= (others => '0');
          else
            if bc_reset = '1' then
              bc_i <= bc_rst_val;
            elsif bc_i = bc_max_val then
              bc_i <= (others => '0');
            else
              bc_i <= bc_i + '1';
            end if;

            -- capture BC at L0
            if l0 = '1' then
              bc_l0_i <= bc_i;
            end if;

            -- determine offset in BC w.r.t. the one sent by CTP
            if l2a = '1' then  -- L2a message valid after L2a seen
              bc_msg_i    <= l2a_msg(95 downto 84);
              bc_offset   <= bc_l0_i - l2a_msg(95 downto 84);
            end if;
          end if;
        end if;
    end process;

  end;