library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity ctp_tin is
  generic (
    signature : std_logic_vector(6 downto 0) := conv_std_logic_vector(83, 7)
  );
  port (
    clk40 : in std_logic;
    rst40 : in std_logic;

    opt_code : in std_logic_vector(1 downto 0);

    trg_ctb : in std_logic;
    rnd_trg : in std_logic;

    trg_out : out std_logic
  );
end ctp_tin;

architecture behav of ctp_tin is

  signal trg_i : std_logic;
  signal trg_out_i : std_logic;

  signal sign_serial : std_logic;
  signal send_sign : std_logic;
  signal send_sign_r : std_logic;
  signal pload : std_logic;
  signal cnt_sign  : std_logic_vector(9 downto 0);

begin

  --
  -- output mapping
  trg_out <= not trg_i;

  process (clk40)
  begin
    if rising_edge(clk40) then
      if rst40 = '1' then
        cnt_sign <= (others => '0');
        send_sign_r <= '0';
        trg_out_i <= '1';
      else
        trg_out_i <= not trg_i;

        if (send_sign_r = '0' and send_sign = '1') then
          cnt_sign <= (others => '0');
        else
          cnt_sign <= cnt_sign + '1';
        end if;
        send_sign_r <= send_sign;
      end if;
    end if;
  end process;

  pload <= '1' when cnt_sign = conv_std_logic_vector(1000, 10) else '0';

  sign_shiftreg : entity work.shiftreg_piso
    port map (
      clk40 => clk40,
      rst40 => rst40,

      din => "10110001" & signature & not signature,
      pload => pload,

      sin => '0',
      sout => sign_serial,

      shift => '1'
    );

  --
  -- select trigger signal according to option code
  with opt_code select
    trg_i <= trg_ctb      when "00",
             trg_out_i    when "01",
             sign_serial  when "10",
             rnd_trg      when "11",
             trg_ctb      when others;

  send_sign <= '1' when opt_code = "10" else '0';

end;