library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity cbb_top is generic ( no_bcmasks : integer := 1; trg_cnt_width : integer := 12 ); port ( RST_n : in std_logic; -- power up reset from the DS1818 -- clock inputs CLK40in : in std_logic; CLK40out : out std_logic; CLK40out_90 : out std_logic; CLK40out_180: out std_logic; CLK40out_270: out std_logic; CLK80out : out std_logic; -- SCSN I/O to DCS board SCSNIN : in std_logic; SCSNOUT : out std_logic; SCSNFEBIN : in std_logic; SCSNFEBOUT : out std_logic; -- SCSN I/O to TLMU IF17x_SCSN_IN : in std_logic; IF17x_SCSN_OUT : out std_logic; -- TTCrx L1ACCEPT : in std_logic; B_Channel : in std_logic; IO_C : in std_logic_vector(1 downto 0); -- SOR/EOR signal from DCS board -- TTCex A_ECL : out std_logic; B_ECL : out std_logic; BC_ECL : out std_logic; -- PIM PIMLINK : out std_logic_vector(2 downto 0); -- GTU GTU_BUSY : in std_logic_vector(1 downto 0); -- TLMU interface CLK40T : out std_logic; RESET_TOFFPGA : out std_logic; CNRRL : out std_logic; -- enable for TLMU interface -- used for primary/backup switching SPA : out std_logic; -- spare: used for SOR/EOR signalling -- TLMU trigger inputs TLMU_trg : in std_logic_vector(7 downto 0); TLMU_trg_f : in std_logic_vector(7 downto 0); -- falling edge data -- input from CB-A/C CB_A : in std_logic_vector(1 downto 0); CB_C : in std_logic_vector(1 downto 0); -- Front-Panel LEDs LED : out std_logic_vector(1 to 2); -- unused SPC : in std_logic; SPD : in std_logic; CB_TOF : out std_logic; -- ??? L_OUTSP : out std_logic; -- spare to TLMU SPB : out std_logic; -- spare to TLMU S1_IN : in std_logic_vector(1 to 2); S1_OUT : out std_logic_vector(1 to 2); S2_IN : in std_logic_vector(1 to 2); S2_OUT : out std_logic_vector(1 to 2) ); end cbb_top; architecture struct of cbb_top is component bc_cnt is port ( clk : in std_logic; rst : in std_logic; bc_reset : in std_logic; l0 : in std_logic; l2a : in std_logic; l2a_msg : in std_logic_vector(95 downto 0); bc : out std_logic_vector(11 downto 0); bc_offset : out std_logic_vector(11 downto 0); bc_l0 : out std_logic_vector(11 downto 0); bc_msg : out std_logic_vector(11 downto 0); bc_rst_val : in std_logic_vector(11 downto 0); bc_max_val : in std_logic_vector(11 downto 0) ); end component; component del_coinc_cnt_en is generic ( depth : integer := 6; ref_offset : integer := 2 ); port ( clk40 : in std_logic; rst40 : in std_logic; enable : in std_logic; ref : in std_logic; sig : in std_logic; cnt_en : out std_logic_vector(depth-1 downto 0) ); end component; component ctp_tin is generic ( signature : std_logic_vector(6 downto 0) := conv_std_logic_vector(83, 7) ); port ( clk40 : in std_logic; rst40 : in std_logic; opt_code : in std_logic_vector(1 downto 0); trg_ctb : in std_logic; rnd_trg : in std_logic; trg_out : out std_logic ); end component; component busy is port ( clk : in std_logic; rst : in std_logic; clk80 : in std_logic; rst80 : in std_logic; busy_gtu_ddr : in std_logic_vector(1 downto 0); ctrl : in std_logic_vector(3 downto 0); -- control signal for busy -- bit 0: 0: ignore -- 1: use GTU busy -- bit 2..1: select edge busy_mon : out std_logic; busy_out : out std_logic ); end component; component pt_align is generic ( no_inputs : integer := 15; no_delays : integer := 8 ); port ( clk : in std_logic; rst : in std_logic; trg_src : in std_logic_vector(15 downto 0); trg_ctb : out std_logic_vector(15 downto 0); trg_ctb_r : out std_logic_vector(15 downto 0); trg_req : out std_logic; trg_req_r : out std_logic; trg_delays : in std_logic_vector(63 downto 0); trg_mask : in std_logic_vector(15 downto 0) ); end component; component ttcex_out is port ( clk : in std_logic; rst : in std_logic; a_channel : in std_logic; b_channel : in std_logic; a_channel_out : out std_logic; b_channel_out : out std_logic; ctrl : in std_logic_vector(15 downto 0) ); end component; component ibuf is port ( I : in std_logic; O : out std_logic); end component; component iddr2 is port ( CE : in std_logic; R : in std_logic; S : in std_logic; -- dummy C0 : in std_logic; -- clock C1 : in std_logic; -- not clock, dummy D : in std_logic; -- d for rising edge Q0 : out std_logic; Q1 : out std_logic); end component; component obuf is port ( I : in std_logic; O : out std_logic); end component; component oddr2 is port ( CE : in std_logic; R : in std_logic; S : in std_logic; -- dummy C0 : in std_logic; -- clock C1 : in std_logic; -- not clock, dummy D0 : in std_logic; -- d for rising edge D1 : in std_logic; -- d for falling edge Q : out std_logic); end component; component ibufds is port ( I : in std_logic; IB : in std_logic; O : out std_logic); end component; component obufds is port ( I : in std_logic; O : out std_logic; OB : out std_logic); end component; component CLKBUF_LVDS port( PADP : in STD_ULOGIC; PADN : in STD_ULOGIC; Y : out STD_ULOGIC); end COMPONENT; --pragma synthesis_off COMPONENT ram_cnt_checker IS generic(Na : Positive := 7; logfile : string := "./compare.log"); port( clk : in std_logic; rst : in std_logic; inputs : in std_logic_vector(2**Na-1 downto 0); inp_msk : in std_logic_vector(2**Na-1 downto 0); track : in std_logic; clear : in std_logic; ack : in std_logic; raddr : in std_logic_vector(15 downto 0); rdata_s : in std_logic_vector(31 downto 0)); END COMPONENT; --pragma synthesis_on -- Clocks and Reset signal clk40 : std_logic; signal clk40_90 : std_logic; signal clk40_180 : std_logic; signal clk40_270 : std_logic; signal clk40_ps : std_logic; signal clk40_ps_180 : std_logic; signal clk80 : std_logic; signal clk80_180 : std_logic; signal clk_scsn : std_logic; signal rst_request : std_logic; -- asynchr. reset request signal rst_request_n : std_logic; signal rst40 : std_logic; signal rst40_n : std_logic; signal rst80 : std_logic; signal rst_scsn : std_logic; signal rst_scsn_n : std_logic; -- SCSN signal scsn_in : std_logic; signal scsn_out : std_logic; signal scsn_feb_in : std_logic; signal scsn_feb_out : std_logic; -- SCSN bus signal scsn_bus_addr : std_logic_vector(15 downto 0); signal scsn_bus_din : std_logic_vector(31 downto 0); signal scsn_bus_dout : std_logic_vector(31 downto 0); signal scsn_bus_we : std_logic; signal scsn_bus_req : std_logic; signal scsn_bus_ack : std_logic; -- signal scsn_bus_din_i : std_logic_vector(31 downto 0); -- bus registers signal scsn_bus_din_ta : std_logic_vector(31 downto 0); signal scsn_bus_din_ramcnt : std_logic_vector(31 downto 0); signal scsn_bus_din_lut : std_logic_vector(31 downto 0); signal scsn_bus_din_bctrg : std_logic_vector(31 downto 0); signal scsn_bus_din_tlrec : std_logic_vector(31 downto 0); signal scsn_bus_dout_r : std_logic_vector(31 downto 0); signal scsn_bus_addr_r : std_logic_vector(15 downto 0); -- signal scsn_bus_we_r : std_logic; signal scsn_bus_we_ramcnt : std_logic; signal scsn_bus_we_lut : std_logic; signal scsn_bus_we_ta : std_logic; signal scsn_bus_we_bctrg : std_logic; signal scsn_bus_we_tlrec : std_logic; signal scsn_bus_req_ramcnt : std_logic; signal scsn_bus_req_lut : std_logic; signal scsn_bus_req_ta : std_logic; signal scsn_bus_req_bctrg : std_logic; signal scsn_bus_req_tlrec : std_logic; -- signal scsn_bus_ack_i : std_logic; signal scsn_bus_ack_ramcnt : std_logic; signal scsn_bus_ack_lut : std_logic; signal scsn_bus_ack_ta : std_logic; signal scsn_bus_ack_bctrg : std_logic; signal scsn_bus_ack_tlrec : std_logic; -- TTC input (from TTCrx) signal ttc_a_channel : std_logic; signal ttc_b_channel : std_logic; -- trigger inputs/requests signal cba_in : std_logic_vector(1 downto 0); signal cbc_in : std_logic_vector(1 downto 0); signal cba_sampling : std_logic_vector(1 downto 0); signal cbc_sampling : std_logic_vector(1 downto 0); signal cba_lut : std_logic_vector(3 downto 0); signal cbc_lut : std_logic_vector(3 downto 0); -- signal tlmu_trg_r : std_logic_vector(7 downto 0); signal pt_req : std_logic; signal pt_req_r : std_logic; signal pt_trg_src : std_logic_vector(15 downto 0); signal pt_trg_ctb : std_logic_vector(15 downto 0); signal pt_trg_ctb_r : std_logic_vector(15 downto 0); signal pt_trg_lut : std_logic_vector(12 downto 0); subtype pt_cba_t is natural range 15 downto 14; subtype pt_cbc_t is natural range 13 downto 12; subtype pt_rnd_t is natural range 11 downto 11; subtype pt_bc_t is natural range 10+(no_bcmasks-1) downto 10; subtype pt_tlmu_t is natural range 9 downto 2; subtype pt_lut_t is natural range 1 downto 0; -- LUT signal pattern_cba : std_logic_vector(1 downto 0); signal pattern_cbc : std_logic_vector(1 downto 0); signal pattern_tof : std_logic_vector(7 downto 0); signal pattern_match_cba : std_logic; signal pattern_match_cbc : std_logic; signal pattern_match_tof : std_logic; signal lut_mon : std_logic_vector(12 downto 0); signal lut_trg : std_logic_vector(1 downto 0); -- trigger pulses signal trg_bc : std_logic_vector(no_bcmasks-1 downto 0); signal rnd_trg : std_logic_vector(0 downto 0); signal pt_to_sm : std_logic; signal l0_to_sm : std_logic; signal l1_to_sm : std_logic; signal l0_ctb : std_logic; signal l0_to_ctp : std_logic; signal busy_i : std_logic; signal busy_mon : std_logic; -- output to TTCex signal a_channel_out : std_logic; signal a_channel_out_masked : std_logic; signal b_channel_out : std_logic; signal a_channel_ttcex_trggen : std_logic; signal ttcex_ctrl : std_logic_vector(1 downto 0); signal ttcex_status : std_logic_vector(9 downto 0); -- GTU signal gtu_busy_ctrl : std_logic_vector(3 downto 0); -- output to PIM signal tin1_out : std_logic; signal tin1_opt_code : std_logic_vector(1 downto 0); signal tin2_out : std_logic; signal tin2_opt_code : std_logic_vector(1 downto 0); signal tin3_out : std_logic; signal tin3_opt_code : std_logic_vector(1 downto 0); -- configuration settings signal cbb_ctrl : std_logic_vector(1 downto 0); signal ptrg_to_l0_acc : std_logic_vector(trg_cnt_width-1 downto 0); signal ptrg_to_l0_send : std_logic_vector(trg_cnt_width-1 downto 0); signal ptrg_to_l1_acc : std_logic_vector(trg_cnt_width-1 downto 0); signal ptrg_to_l1_send : std_logic_vector(trg_cnt_width-1 downto 0); signal ptrg_to_idle : std_logic_vector(trg_cnt_width-1 downto 0); signal ptrg_to_idle_nol0 : std_logic_vector(trg_cnt_width-1 downto 0); signal ptrg_to_idle_nol1 : std_logic_vector(trg_cnt_width-1 downto 0); signal ptrg_to_l0_delay : std_logic_vector(trg_cnt_width-1 downto 0); signal a_channel_out_dis : std_logic; signal pt_trg_mask : std_logic_vector(15 downto 0); signal pt_trg_delays : std_logic_vector(63 downto 0); signal rnd_trg_thr : std_logic_vector(31 downto 0); signal tana_trg_mask : std_logic_vector(31 downto 0); signal tana_trg_val : std_logic_vector(31 downto 0); signal tana_arm : std_logic; signal tana_postcnt : std_logic_vector(8 downto 0); -- TTC output control signal ttc_channel_ctrl : std_logic_vector(15 downto 0); -- BC signal bc : std_logic_vector(11 downto 0); signal bc_rst_val : std_logic_vector(11 downto 0) := conv_std_logic_vector( 0, 12); constant bc_max_val : std_logic_vector(11 downto 0) := conv_std_logic_vector(3563, 12); signal bc_l0 : std_logic_vector(11 downto 0); signal bc_msg : std_logic_vector(11 downto 0); signal bc_offset : std_logic_vector(11 downto 0); -- TTC receiver signal l0_ttcrx : std_logic; signal l1_ttcrx : std_logic; signal l2a_ttcrx : std_logic; signal l2r_ttcrx : std_logic; signal l1m_ttcrx : std_logic; signal l2m_ttcrx : std_logic; signal sod_ttcrx : std_logic; signal eod_ttcrx : std_logic; signal rst_bunch_counter_ttcrx : std_logic; signal rst_event_counter_ttcrx : std_logic; signal l1_message_ttcrx : std_logic_vector(59 downto 0); signal l1_message_rdy_ttcrx : std_logic; signal l2a_message_ttcrx : std_logic_vector(95 downto 0); signal l2r_message_ttcrx : std_logic_vector(11 downto 0); -- from emulator signal pt_emu : std_logic; signal pt_ctp : std_logic; signal l0_emu : std_logic; signal l1_emu : std_logic; -- trigger counters signal ram_cnt_clr : std_logic; signal ram_cnt_capt : std_logic; signal ram_cnt_input : std_logic_vector(127 downto 0); signal ram_cnt_in_msk: std_logic_vector(127 downto 0); signal tlmu_trg_a_c : std_logic_vector(7 downto 0); signal tlmu_trg_nota_c : std_logic_vector(7 downto 0); signal tlmu_trg_a_notc : std_logic_vector(7 downto 0); signal tlmu_trg_nota_notc : std_logic_vector(7 downto 0); signal cba_coinc_cnt_en : std_logic_vector(7 downto 0); signal cbc_coinc_cnt_en : std_logic_vector(7 downto 0); signal coinc_cnt_ctrl : std_logic_vector(31 downto 0); signal ac_short: std_logic_vector(1 downto 0); begin -- default -- -- signal mappings -- reset request from SCSN or external source rst_request <= not rst_request_n or not RST_n; ram_cnt_in_msk <= (others => '1'); -- dummy signal SPA <= IO_C(0) xor IO_C(1) xor S1_in(2) xor S1_in(1) xor S2_in(2) xor S2_in(1) xor SPC xor SPD; CB_TOF <= '0'; L_OUTSP <= '0'; -- front panel LEDs LED(1) <= '1'; LED(2) <= '0'; -- signals to TTCex BC_ECL <= '1'; -- oddr, clock comes from ODDR A_ECL <= a_channel_out; B_ECL <= b_channel_out; -- SCSN scsn_feb_in <= SCSNFEBIN; scsn_in <= SCSNIN; SCSNFEBOUT <= scsn_feb_out; SCSNOUT <= scsn_out; -- TTCrx input ttc_a_channel <= L1ACCEPT; ttc_b_channel <= B_Channel; -- optical input from CB-A/C cba_in <= CB_A; cbc_in <= CB_C; -- clock outputs clk40out <= clk40; clk40out_90 <= clk40_90; clk40out_180 <= clk40_180; clk40out_270 <= clk40_270; CLK40T <= clk40; clk80out <= clk80; -- GTU -- in adjacent cell to CB-A => sharing I/O resources => same clocks must -- be used for DDR cells -- TLMU RESET_TOFFPGA <= rst40 when cbb_ctrl(1) = '0' else rst40_n; CNRRL <= cbb_ctrl(0); -- enable signal for TLMU LVDS buffers SPB <= not cbb_ctrl(0); -- enable signal for TLMU (active low) -- PIM (goes to ODDR) PIMLINK <= tin2_out & tin1_out & '1'; -- direct LVDS link to CTP LM inputs S1_out <= not tin2_out & not tin3_out; S2_out <= not tin2_out & not tin3_out; -- SCSN forwarding scsn_feb_out <= IF17x_SCSN_IN; IF17x_SCSN_OUT <= scsn_feb_in; -- RAM counter inputs ram_cnt_input( 3 downto 0) <= l1_ttcrx & l0_ttcrx & '0' & "1"; ram_cnt_input( 7 downto 4) <= ttc_b_channel & ttc_a_channel & rst_bunch_counter_ttcrx & rst_event_counter_ttcrx; ram_cnt_input( 11 downto 8) <= l2r_ttcrx & l2a_ttcrx & l1_ttcrx & l0_ttcrx ; ram_cnt_input( 15 downto 12) <= cba_in(0) & cba_in(0) & '0' & '0'; ram_cnt_input( 19 downto 16) <= lut_mon(3 downto 0); ram_cnt_input( 23 downto 20) <= lut_mon(7 downto 4); ram_cnt_input( 27 downto 24) <= tlmu_trg(3 downto 0); ram_cnt_input( 31 downto 28) <= tlmu_trg(7 downto 4); ram_cnt_input( 35 downto 32) <= '0' & pattern_match_tof & pattern_match_cbc & pattern_match_cba; ram_cnt_input( 39 downto 36) <= "0000"; ram_cnt_input( 43 downto 40) <= '0' & pt_emu & l0_emu & l1_emu; ram_cnt_input( 47 downto 44) <= "00" & '1' & a_channel_out_masked; ram_cnt_input( 51 downto 48) <= l0_to_ctp & '1' & rnd_trg(0) & trg_bc(0); ram_cnt_input( 55 downto 52) <= l1_to_sm & l0_to_sm & pt_to_sm & a_channel_ttcex_trggen; ram_cnt_input( 59 downto 56) <= '0' & pt_req & lut_trg(0) & lut_trg(1); ram_cnt_input( 63 downto 60) <= "0000"; ram_cnt_input( 71 downto 64) <= tlmu_trg_a_c; ram_cnt_input( 79 downto 72) <= tlmu_trg_a_notc; ram_cnt_input( 87 downto 80) <= tlmu_trg_nota_c; ram_cnt_input( 95 downto 88) <= tlmu_trg_nota_notc; ram_cnt_input(103 downto 96) <= cba_coinc_cnt_en; ram_cnt_input(111 downto 104) <= cbc_coinc_cnt_en; ram_cnt_input(113 downto 112) <= busy_i & busy_mon; ram_cnt_input(119 downto 114) <= (others => '1'); ram_cnt_input(123 downto 120) <= cba_lut(3 downto 0); ram_cnt_input(127 downto 124) <= cbc_lut(3 downto 0); -- -- combinatorial logic for timing analyzer and counters tlmu_trg_a_c <= pt_trg_ctb_r(pt_tlmu_t) when pt_trg_ctb_r(pt_bc_t'low) = '1' and pattern_match_cba = '1' and pattern_match_cbc = '1' else x"00"; tlmu_trg_a_notc <= pt_trg_ctb_r(pt_tlmu_t) when pt_trg_ctb_r(pt_bc_t'low) = '1' and pattern_match_cba = '1' and pattern_match_cbc = '0' else x"00"; tlmu_trg_nota_c <= pt_trg_ctb_r(pt_tlmu_t) when pt_trg_ctb_r(pt_bc_t'low) = '1' and pattern_match_cba = '0' and pattern_match_cbc = '1' else x"00"; tlmu_trg_nota_notc <= pt_trg_ctb_r(pt_tlmu_t) when pt_trg_ctb_r(pt_bc_t'low) = '1' and pattern_match_cba = '0' and pattern_match_cbc = '0' else x"00"; -- -- clock & reset generation clock_generation : entity work.clock_gen port map ( clk40i => clk40in, rst_req => rst_request, clk40 => clk40, clk40_90 => clk40_90, clk40_180 => clk40_180, clk40_270 => clk40_270, clk80 => clk80, clk80_180 => clk80_180, clk_scsn => clk_scsn, rst_scsn => rst_scsn, rst_scsn_n => rst_scsn_n, -- ps_adjust => ttcex_ctrl(1 downto 0), -- ps_state => ttcex_status(9 downto 0), clk40_ps => clk40_ps, clk40_ps_180 => clk40_ps_180, rst40 => rst40, rst40_n => rst40_n, rst80 => rst80 ); -- -- SCSN interface scsn_inst : entity work.mcm_network_interface port map ( ser0_din => scsn_in, ser0_dout => scsn_out, ser1_din => '0', ser1_dout => open, bus_din => scsn_bus_din, bus_dout => scsn_bus_dout, bus_addr => scsn_bus_addr, bus_req => scsn_bus_req, bus_we => scsn_bus_we, bus_ack => scsn_bus_ack, chipRST_n => rst_request_n, reset_n => rst_scsn_n, clk => clk_scsn, clk_buf => clk_scsn, clk_buf_disable => open ); -- -- System configuration -- connected to SCSN bus interface sys_config0: entity work.sys_config generic map ( trg_cnt_width => trg_cnt_width ) port map( clk => clk_scsn, rst => rst_scsn, cbb_ctrl => cbb_ctrl, ttc_channel_ctrl => ttc_channel_ctrl, ram_cnt_clr => ram_cnt_clr, ram_cnt_capt => ram_cnt_capt, ptrg_to_l0_acc => ptrg_to_l0_acc, ptrg_to_l0_send => ptrg_to_l0_send, ptrg_to_l1_acc => ptrg_to_l1_acc, ptrg_to_l1_send => ptrg_to_l1_send, ptrg_to_idle => ptrg_to_idle, ptrg_to_idle_nol0 => ptrg_to_idle_nol0, ptrg_to_idle_nol1 => ptrg_to_idle_nol1, ptrg_to_l0_delay => ptrg_to_l0_delay, a_channel_out_dis => a_channel_out_dis, gtu_busy_ctrl => gtu_busy_ctrl, pt_trg_mask => pt_trg_mask, pt_trg_delays => pt_trg_delays, cba_sampling => cba_sampling, cbc_sampling => cbc_sampling, pattern_cba => pattern_cba, pattern_cbc => pattern_cbc, pattern_tof => pattern_tof, bc_offset => bc_offset, bc_l0 => bc_l0, bc_msg => bc_msg, bc_rst_val => bc_rst_val, tin1_opt_code => tin1_opt_code, tin2_opt_code => tin2_opt_code, tin3_opt_code => tin3_opt_code, tim_ana_trg_mask => tana_trg_mask, tim_ana_trg_val => tana_trg_val, tim_ana_arm => tana_arm, tim_ana_postcnt => tana_postcnt, rnd_trg_thr => rnd_trg_thr, coinc_cnt_ctrl => coinc_cnt_ctrl, ttcex_ctrl => ttcex_ctrl, ttcex_status => ttcex_status, debug(31 downto 8) => x"000000", debug( 7 downto 0) => tlmu_trg, -- syscfg_addr => scsn_bus_addr_r, -- syscfg_wdata => scsn_bus_dout_r, -- syscfg_rdata => scsn_bus_din_i, -- syscfg_req => scsn_bus_req_r, -- syscfg_ack => scsn_bus_ack_i, -- syscfg_we => scsn_bus_we_r, scsn_addr => scsn_bus_addr, scsn_dout => scsn_bus_dout, scsn_din => scsn_bus_din, scsn_req => scsn_bus_req, scsn_ack => scsn_bus_ack, scsn_we => scsn_bus_we, scsn_dout_com => scsn_bus_dout_r, scsn_addr_com => scsn_bus_addr_r, scsn_we_ta => scsn_bus_we_ta, scsn_req_ta => scsn_bus_req_ta, scsn_ack_ta => scsn_bus_ack_ta, scsn_din_ta => scsn_bus_din_ta, scsn_addr_ta => open, scsn_we_ramcnt => scsn_bus_we_ramcnt, scsn_req_ramcnt => scsn_bus_req_ramcnt, scsn_ack_ramcnt => scsn_bus_ack_ramcnt, scsn_din_ramcnt => scsn_bus_din_ramcnt, scsn_addr_ramcnt => open, scsn_we_lut => scsn_bus_we_lut, scsn_req_lut => scsn_bus_req_lut, scsn_ack_lut => scsn_bus_ack_lut, scsn_din_lut => scsn_bus_din_lut, scsn_addr_lut => open, scsn_we_bctrg => scsn_bus_we_bctrg, scsn_req_bctrg => scsn_bus_req_bctrg, scsn_ack_bctrg => scsn_bus_ack_bctrg, scsn_din_bctrg => scsn_bus_din_bctrg, scsn_addr_bctrg => open, scsn_we_tlrec => scsn_bus_we_tlrec, scsn_req_tlrec => scsn_bus_req_tlrec, scsn_ack_tlrec => scsn_bus_ack_tlrec, scsn_din_tlrec => scsn_bus_din_tlrec, scsn_addr_tlrec => open ); -- -- CB-A/C sampling cba_sample: entity work.cb_ac_sample port map( clk40 => clk40, rst40 => rst40, clk80 => clk80, rst80 => rst80, cb_sample_par => cba_sampling, cb_in => cba_in, cb_out => cba_lut ); cbc_sample: entity work.cb_ac_sample port map( clk40 => clk40, rst40 => rst40, clk80 => clk80, rst80 => rst80, cb_sample_par => cbc_sampling, cb_in => cbc_in, cb_out => cbc_lut ); -- -- busy logic, using GTU busy busy_inst : busy port map ( clk => clk40, rst => rst40, clk80 => clk80, rst80 => rst80, busy_gtu_ddr => gtu_busy, ctrl => gtu_busy_ctrl, busy_mon => busy_mon, busy_out => busy_i ); -- -- LUT pt_trg_lut <= pt_trg_ctb(pt_cba_t) & pt_trg_ctb(pt_cbc_t) & pt_trg_ctb(pt_bc_t) & pt_trg_ctb(pt_rnd_t) & pt_trg_ctb(pt_tlmu_t'high-1 downto pt_tlmu_t'low); trg_lut_inst: entity work.trg_lut port map( clk40 => clk40, rst40 => rst40, trg_ctb => pt_trg_lut, pattern_tof => pattern_tof, pattern_cba => pattern_cba, pattern_cbc => pattern_cbc, pattern_match_tof => pattern_match_tof, pattern_match_cba => pattern_match_cba, pattern_match_cbc => pattern_match_cbc, lut_mon => lut_mon, trigger => lut_trg, scsn_addr => scsn_bus_addr_r, scsn_din => scsn_bus_dout_r, scsn_we => scsn_bus_we_lut, scsn_req => scsn_bus_req_lut, scsn_dout => scsn_bus_din_lut, scsn_ack => scsn_bus_ack_lut ); -- -- PT contribution pt_trg_src(pt_cba_t) <= cba_lut(2) & cba_lut(0); pt_trg_src(pt_cbc_t) <= cbc_lut(2) & cbc_lut(0); pt_trg_src(pt_rnd_t) <= rnd_trg; pt_trg_src(pt_bc_t) <= trg_bc; pt_trg_src(pt_tlmu_t) <= tlmu_trg; pt_trg_src(pt_lut_t) <= lut_trg; pt_align_inst : pt_align port map ( clk => clk40, rst => rst40, trg_src => pt_trg_src, trg_ctb => pt_trg_ctb, trg_ctb_r => pt_trg_ctb_r, trg_req => pt_req, trg_req_r => pt_req_r, trg_delays => pt_trg_delays, trg_mask => pt_trg_mask ); -- -- trigger emulation (insert missing pretrigger) trg_emu : entity work.trg_emulator generic map ( cnt_width => trg_cnt_width ) port map ( clk40 => clk40, rst40 => rst40, pt_in => pt_req, l0_in => l0_ttcrx, l1_in => l1_ttcrx, pt_out => pt_emu, pt_ctp => pt_ctp, l0_out => l0_emu, l1_out => l1_emu, trg_delay => ptrg_to_l0_delay ); -- -- trigger sequence generation trg_gen : entity work.trg_generator generic map ( cnt_width => trg_cnt_width ) port map ( clk40 => clk40, rst40 => rst40, pt_in => pt_req_r, pt_ctp => pt_req_r, l0_in => l0_ttcrx, l1_in => l1_ttcrx, pt_in_emu => pt_emu, pt_ctp_emu => pt_ctp, l0_in_emu => l0_emu, l1_in_emu => l1_emu, pt_to_sm => pt_to_sm, l0_to_sm => l0_to_sm, l1_to_sm => l1_to_sm, l0_to_ctp => l0_to_ctp, busy => busy_i, use_emu => ttc_channel_ctrl(8), send_pt_to_ctp => ttc_channel_ctrl(9), ptrg_to_l0_acc => ptrg_to_l0_acc, ptrg_to_l0_send => ptrg_to_l0_send, ptrg_to_l1_acc => ptrg_to_l1_acc, ptrg_to_l1_send => ptrg_to_l1_send, ptrg_to_idle_nol0 => ptrg_to_idle_nol0, ptrg_to_idle_nol1 => ptrg_to_idle_nol1, ptrg_to_idle => ptrg_to_idle ); a_channel_ttcex_trggen <= (pt_to_sm or l0_to_sm or l1_to_sm) when ttc_channel_ctrl(4) = '0' else (l0_ttcrx or l1_ttcrx); -- -- random trigger pulse generator rnd_trg_inst : entity work.random_pulser port map ( clk40 => clk40, rst40 => rst40, thr => rnd_trg_thr, pulse => rnd_trg(0) ); -- -- output to TTCex a_channel_out_masked <= a_channel_ttcex_trggen and not a_channel_out_dis; ttcex_out_inst : ttcex_out port map ( clk => clk40, rst => rst40, a_channel => a_channel_out_masked, b_channel => '1', a_channel_out => a_channel_out, b_channel_out => b_channel_out, ctrl => ttc_channel_ctrl ); -- -- output to CTP via PIM tin1_inst : ctp_tin generic map ( signature => conv_std_logic_vector(83, 7) ) port map ( clk40 => clk40, rst40 => rst40, opt_code => tin1_opt_code, trg_ctb => l0_to_ctp, rnd_trg => rnd_trg(0), trg_out => tin1_out ); tin2_inst : entity work.ctp_tin generic map ( signature => conv_std_logic_vector(82, 7) ) port map ( clk40 => clk40, rst40 => rst40, opt_code => tin2_opt_code, trg_ctb => pt_req_r, rnd_trg => rnd_trg(0), trg_out => tin2_out ); tin3_inst : entity work.ctp_tin generic map ( signature => conv_std_logic_vector(84, 7) ) port map ( clk40 => clk40, rst40 => rst40, opt_code => tin3_opt_code, trg_ctb => TLMU_trg(0), rnd_trg => rnd_trg(0), trg_out => tin3_out ); -- -- TTC receiver ttc_receiver0 : entity work.ttc_receiver_top port map ( -- general signals clk => clk40, reset_n => rst40_n, -- -- ttc event logging & communication -- clk_ppc : in std_logic; -- ttc_events_addr : in std_logic_vector(9 downto 0); -- ttc_events_data : out std_logic_vector(17 downto 0); -- ttc_events_log_ctrl : in std_logic_vector(19 downto 0); -- ttc_events_log_mon : out std_logic_vector(15 downto 0); -- ttc_events_log_halt : in std_logic; channelA => ttc_a_channel, channelB => ttc_b_channel, -- triggers l0trigger => l0_ttcrx, l1trigger => l1_ttcrx, l2atrigger => l2a_ttcrx, l2rtrigger => l2r_ttcrx, -- strobes l1m_strobe => l1m_ttcrx, l2m_strobe => l2m_ttcrx, -- sod/eod sod => sod_ttcrx, eod => eod_ttcrx, sod_eod_debug_up => open, -- resets reset_bc => rst_bunch_counter_ttcrx, reset_ec => rst_event_counter_ttcrx, error_ttc_rcv => open, -- message outputs l1_message => l1_message_ttcrx, l1_message_rdy => l1_message_rdy_ttcrx, l2a_message => l2a_message_ttcrx, l2r_message => l2r_message_ttcrx ); -- BC counter -- reset comes via TTC bc_cnt_inst : bc_cnt port map ( clk => clk40, rst => rst40, bc_reset => rst_bunch_counter_ttcrx, l0 => l0_ttcrx, l2a => l2a_ttcrx, l2a_msg => l2a_message_ttcrx, bc => bc, bc_offset => bc_offset, bc_l0 => bc_l0, bc_msg => bc_msg, bc_rst_val => bc_rst_val, bc_max_val => bc_max_val ); -- -- BC trigger bc_trigger_inst : entity work.bc_trigger generic map ( no_bcmasks => no_bcmasks ) port map ( clk40 => clk40, rst40 => rst40, clk_scsn => clk_scsn, rst_scsn => rst_scsn, scsn_addr => scsn_bus_addr_r(11 downto 0), scsn_din => scsn_bus_dout_r, scsn_dout => scsn_bus_din_bctrg, scsn_req => scsn_bus_req_bctrg, scsn_ack => scsn_bus_ack_bctrg, scsn_we => scsn_bus_we_bctrg, bc => bc, trg => trg_bc ); -- -- Timing Coinc Counters cba_coinc_cnt: del_coinc_cnt_en generic map ( depth => 8, ref_offset => 6 ) port map ( clk40 => clk40, rst40 => rst40, enable => coinc_cnt_ctrl(0), ref =>trg_bc(0), sig => ac_short(0), cnt_en=>cba_coinc_cnt_en(7 downto 0) ); cbc_coinc_cnt: del_coinc_cnt_en generic map ( depth => 8, ref_offset => 6 ) port map ( clk40 => clk40, rst40 => rst40, enable => coinc_cnt_ctrl(1), ref =>trg_bc(0), sig => ac_short(1), cnt_en=>cbc_coinc_cnt_en(7 downto 0) ); -- -- RAM counters ram_cnt_inst : entity work.ram_cnt port map ( clk => clk40, rst => rst40, capture => ram_cnt_capt, clear => ram_cnt_clr, inputs => ram_cnt_input, input_mask => ram_cnt_in_msk, scsn_addr => scsn_bus_addr_r, scsn_dout => scsn_bus_din_ramcnt, scsn_req => scsn_bus_req_ramcnt, scsn_ack => scsn_bus_ack_ramcnt ); --pragma synthesis_off --pragma translate_off ram_cnt_check: ram_cnt_checker --generic(Na : Positive := 7; -- logfile : string := "./DATA/compare.log"); port map( clk => clk40, rst => rst40, inputs => ram_cnt_input, inp_msk => ram_cnt_in_msk, track => ram_cnt_capt, clear => ram_cnt_clr, ack => scsn_bus_ack_ramcnt, raddr => scsn_bus_addr_r, rdata_s => scsn_bus_din_ramcnt); --pragma synthesis_on --pragma translate_on -- -- Timing analyzer tim_ana : entity work.timing_analyzer port map ( clk40 => clk40, rst40 => rst40, clk_scsn => clk_scsn, rst_scsn => rst_scsn, signals(0) => l0_ttcrx, signals(1) => l1_ttcrx, signals(2) => l0_to_ctp, signals(3) => tin1_out, signals(4) => l0_ctb, signals(5) => pt_to_sm, signals(6) => l0_to_sm, signals(7) => l1_to_sm, signals(8) => pt_req, signals(9) => pt_trg_ctb_r(pt_bc_t'low), -- trg_bc, signals(10) => pt_trg_ctb_r(pt_rnd_t'low), -- rnd_trg, signals(18 downto 11) => pt_trg_ctb_r(pt_tlmu_t), -- tlmu_trg, signals(20 downto 19) => pt_trg_ctb(pt_lut_t), -- lut_trg, signals(21) => pt_emu, signals(22) => pt_ctp, signals(23) => l0_emu, signals(24) => l1_emu, signals(25) => a_channel_out, signals(27 downto 26) => pt_trg_ctb_r(pt_cba_t), -- cba_lut_r, signals(29 downto 28) => pt_trg_ctb_r(pt_cbc_t), -- cbc_lut_r, signals(30) => busy_mon, -- signals(11 downto 0) => scsn_bus_dout(11 downto 0), -- signals(23 downto 12) => scsn_bus_addr(11 downto 0), -- signals(24) => scsn_bus_req, -- signals(25) => scsn_bus_ack, -- signals(26) => scsn_bus_we, -- signals(27) => scsn_bus_we_bctrg, -- signals(30 downto 28) => "000", trg_mask => tana_trg_mask(30 downto 0), trg_val => tana_trg_val(30 downto 0), arm => tana_arm, post_cnt => tana_postcnt, status => open, scsn_addr => scsn_bus_addr_r, scsn_req => scsn_bus_req_ta, scsn_data => scsn_bus_din_ta, scsn_ack => scsn_bus_ack_ta ); -- tlmureceiver cbbr_top_1: entity work.cbbr_top generic map ( clkratio => 1) port map ( clk40 => clk40, reset_n => rst40_n, address => scsn_bus_addr_r(3 downto 0), cbbr_IBO => scsn_bus_dout_r, cbbr_OBI => scsn_bus_din_tlrec, we => scsn_bus_we_tlrec, ack => scsn_bus_ack_tlrec, req => scsn_bus_req_tlrec, din => tlmu_trg, dinf => tlmu_trg_f, do => open, do_strobe => open); end;