library IEEE;
use IEEE.std_logic_1164.all;
use std.textio.all;

entity trg_generator_tb is 
  generic (
    trg_stim_file : string := "trg_stim.txt"
  );

end trg_generator_tb;    

architecture default of trg_generator_tb is

  constant clk40_period : time := 25 ns;

  signal clk40 : std_logic;

  signal pretrigger : std_logic;
  signal l0 : std_logic;
  signal l1 : std_logic;
  
  signal pt_to_sm : std_logic;
  signal l0_to_sm : std_logic;
  signal l1_to_sm : std_logic;
  
  signal trg_to_sm : std_logic;
  signal trg_to_ctp : std_logic;

  file trg_stim : text open read_mode is trg_stim_file;

begin  -- default

  -- clock generation
  process
  begin
    clk40 <= '1';
    wait for clk40_period / 2;
    clk40 <= '0';
    wait for clk40_period / 2;
  end process;

  -- file I/O to read trigger stimuli
  process
    variable lin : line;
    variable log : line;
    variable delay : integer;
    variable trg_in : integer;
    variable trg : std_logic_vector(2 downto 0);

  begin
    while not endfile(trg_stim) loop
      readline(trg_stim, lin);
      read(lin, delay);
      read(lin, trg_in);
      write(log, "delay: ");
      write(log, delay);
      write(log, ", trg: ");
      write(log, trg_in);
      writeline(output, log);

      if (trg_in mod 2) /= 0 then
        pretrigger <= '1';
        report "test";
      else
        pretrigger <= '0';
      end if;

      if ((trg_in/2) mod 2) /= 0 then
        l0 <= '1';
      else
        l0 <= '0';
      end if;

      if ((trg_in/4) mod 2) /= 0 then
        l1 <= '1';
      else
        l1 <= '0';
      end if;
      
      wait for (delay + 1) * clk40_period;
      
    end loop;
    wait;
  end process;

  -- instantiation of dut
  dut_trg_generator : entity work.trg_generator port map (
    clk40 => clk40,
    rst40 => '0',

    pt_in => pretrigger,
    pt_ctp => pretrigger,
    l0_in => l0,
    l1_in => l1,

    pt_in_emu  => '0',
    pt_ctp_emu => '0',
    l0_in_emu  => '0',
    l1_in_emu  => '0',

    use_emu    => '0',
    send_pt_to_ctp => '1',
    busy         => '0',

    pt_to_sm => pt_to_sm,
    l0_to_sm => l0_to_sm,
    l1_to_sm => l1_to_sm,

    l0_to_ctp => trg_to_ctp
  );

  trg_to_sm <= pt_to_sm or l0_to_sm or l1_to_sm;

end default;