library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity rnd_trg_tb is

end rnd_trg_tb;

architecture default of rnd_trg_tb is

  signal clk40_period : time := 25 ns;

  signal clk40 : std_logic;
  signal rst40 : std_logic;

  signal rnd_pulse : std_logic;

  signal rnd_thr : std_logic_vector(31 downto 0) := x"02000000";

begin

  process
  begin
    clk40 <= '1';
    wait for clk40_period/2;
    clk40 <= '0';
    wait for clk40_period/2;
  end process;

  process
  begin
    rst40 <= '1';
    wait for 10*clk40_period;
    rst40 <= '0';
    wait;
  end process;

  rnd_trg : entity work.random_pulser
    port map (
      clk40 => clk40,
      rst40 => rst40,

      thr => rnd_thr,

      pulse => rnd_pulse
    );

end default;