library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity ram_cnt_tb is

end ram_cnt_tb;

architecture default of ram_cnt_tb is

  signal clk40_period : time := 25 ns;

  signal clk40 : std_logic;
  signal rst40 : std_logic;

  signal trg : std_logic;

  signal capture : std_logic;
  signal clear : std_logic;

  signal rnd_pulse : std_logic;

  signal rnd_thr : std_logic_vector(31 downto 0) := x"02000000";

  signal read_req : std_logic;

begin

  process
  begin
    clk40 <= '1';
    wait for clk40_period/2;
    clk40 <= '0';
    wait for clk40_period/2;
  end process;

  process
  begin
    rst40 <= '1';
    wait for 5*clk40_period;
    rst40 <= '0';
    wait;
  end process;

  process
  begin
    read_req <= '0';
    wait for 50*clk40_period;
    read_req <= '1';
    wait for clk40_period;
  end process;

  process
  begin
    clear <= '0';
    wait for 100*clk40_period;
    clear <= '0';
    wait for clk40_period;
    clear <= '0';
    wait;
  end process;

  process
  begin
    capture <= '0';
    wait for 343*clk40_period;
    capture <= '1';
    wait for clk40_period;
    capture <= '0';
    wait for 600*clk40_period;
    capture <= '1';
    wait for clk40_period;
    capture <= '0';
    wait;
  end process;

  rnd_trg : entity work.random_pulser
    port map (
      clk40 => clk40,
      rst40 => rst40,

      thr => rnd_thr,

      pulse => rnd_pulse
    );

  trg <= not rnd_pulse;

  ram_cnt_inst : entity work.ram_cnt
    port map (
      clk40 => clk40,
      rst40 => rst40,

      capture => capture,
      clear => clear,

      input_mask => (others => '1'),

      inputs(127 downto 16) => x"800000000000_00000000_00000000",
      inputs(15 downto 2) => x"000" & "00",
      inputs(1) => trg,
      inputs(0) => rnd_pulse,

      scsn_addr => (others => '1'),
      scsn_dout => open,
      scsn_req  => read_req,
      scsn_ack  => open
    );

end default;