vhdl work "./buildstamp.vhd"
vhdl work "../../src/misc/sys_config.vhd"
vhdl work "../../src/misc/shiftreg_piso.vhd"
#vhdl work "../../src/misc/mersenne_twister.vhd"
vhdl work "../../src/misc/random_pulser.vhd"
vhdl work "../../src/ctp_tin.vhd"
vhdl work "../../src/bc_trigger.vhd"
vhdl work "../../src/misc/cb_ac_sample.vhd"
vhdl work "../../src/misc/del_coinc_cnt_en.vhd"

vhdl work "../../src/misc/ram_cnt_cnt.vhd"
vhdl work "../../src/misc/ram_cnt.vhd"
vhdl work "../../src/misc/trg_lut.vhd"

vhdl work "../../src/ttcreceiver/serialb_com.vhd"
vhdl work "../../src/ttcreceiver/channelB_reg.vhd"
vhdl work "../../src/ttcreceiver/ttc_receiver_top.vhd"

vhdl work "../../src/clock_gen.vhd"
vhdl work "../../src/trg_generator.vhd"
vhdl work "../../src/trg_emulator.vhd"
vhdl work "../../src/timing_analyzer.vhd"

vhdl work "../../src/misc/ttcex_out.vhd"
vhdl work "../../src/misc/bc_cnt.vhd"
vhdl work "../../src/misc/pt_align.vhd"
vhdl work "../../src/misc/busy.vhd"

vhdl work "../../src/mcm/mcm_network_interface.vhd"
vhdl work "../../src/mcm/mcm_nw_apl.vhd"
vhdl work "../../src/mcm/mcm_nw_bittiming.vhd"
vhdl work "../../src/mcm/mcm_nw_destuffing.vhd"
vhdl work "../../src/mcm/mcm_nw_dll.vhd"
vhdl work "../../src/mcm/mcm_nw_inbuf.vhd"
vhdl work "../../src/mcm/mcm_nw_nwl.vhd"
vhdl work "../../src/mcm/mcm_nw_nwsl.vhd"
vhdl work "../../src/mcm/mcm_nw_outbuf.vhd"
vhdl work "../../src/mcm/mcm_nw_pl.vhd"
vhdl work "../../src/mcm/mcm_nw_sendtiming.vhd"
vhdl work "../../src/mcm/mcm_nw_stuffing.vhd"
vhdl work "../../src/mcm/mcm_nw_timer.vhd"
vhdl work "../../src/mcm/hamm34enc67.vhd"
vhdl work "../../src/mcm/hamm67dec34.vhd"
vhdl work "../../src/mcm/hamm_reg.vhd"

vhdl work "../../src/tlmureceiver/cbbr_iserdes.vhd"
vhdl work "../../src/tlmureceiver/ucrc_par.vhd"
vhdl work "../../src/tlmureceiver/cbbr_top.vhd"

vhdl work "../../src/cores/psrg.vhd"
vhdl work "../../arch/xilinx/cores/pll40_40d_80.vhd"
vhdl work "../../arch/xilinx/cores/clkbuf_lvds.vhd"
vhdl work "../../arch/xilinx/cores/ram4k_w8_r1.vhd"
vhdl work "../../arch/xilinx/cores/dp_sram_512x32.vhd"
vhdl work "../../arch/xilinx/cores/dp_sram_128x54.vhd"
vhdl work "../../arch/xilinx/cores/lut_8k_2.vhd"

vhdl work "../../src/cbb_top.vhd"
#vhdl work "../../src/top.vhd"
verilog work "../../src/top.v"