library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity pll40_160 is
  port (
    POWERDOWN  : in  std_logic;   -- active high
    CLKA       : in  std_logic;   -- input clock 40 MHz
    LOCK       : out std_logic;   -- locked
    GLA        : out std_logic;   -- 40 MHz
    GLB        : out std_logic    -- 160 MHz
  );
end pll40_160;

architecture default of pll40_160 is

signal clk40_i  : std_logic;
signal clk80_i  : std_logic;

signal clk40_pre_buf : std_logic;
signal clk40_90_pre_buf : std_logic;
signal clk80_pre_buf : std_logic;
signal clk80_180_pre_buf : std_logic;

signal dcm_40_locked : std_logic;

begin

  GLA <= clk40_i;
  GLB <= clk80_i;
  LOCK <= dcm_40_locked;

  -- DCM for generation of clk40 and clk120
  dcm_clk40_80 : DCM_SP
    generic map (
      DLL_FREQUENCY_MODE     => "LOW",
      CLK_FEEDBACK           => "1X",
      DUTY_CYCLE_CORRECTION  => TRUE,
      CLKDV_DIVIDE           => 16.0,
      CLKFX_MULTIPLY         => 3,
      CLKFX_DIVIDE           => 1,
      PHASE_SHIFT            => 0,
      CLKOUT_PHASE_SHIFT     => "NONE",
      DESKEW_ADJUST          => "SOURCE_SYNCHRONOUS",  -- ???
      DFS_FREQUENCY_MODE     => "LOW",  -- ???
      DLL_FREQUENCY_MODE     => "LOW",
      STARTUP_WAIT           => TRUE,
      CLKIN_DIVIDE_BY_2      => FALSE
      )
    port map (
      CLKIN       => CLKA,
      CLKFB       => clk40_i,
      RST         => '0',
      PSEN        => open,
      PSINCDEC    => open,
      PSCLK       => open,
      CLK0        => clk40_pre_buf,
      CLK90       => clk40_90_pre_buf,
      CLK180      => open,  --clk40_180_pre_buf,
      CLK270      => open,
      CLK2X       => clk80_pre_buf,
      CLK2X180    => clk80_180_pre_buf,
      CLKDV       => open,
      CLKFX       => open,  --clk120_pre_buf,
      CLKFX180    => open, --clk120_180_pre_buf,
      STATUS      => open,
      LOCKED      => dcm_40_locked,
      PSDONE      => open
      );

  bufg_clk40     : BUFG    port map ( I => clk40_pre_buf, O => clk40_i );
--  bufg_clk40_90  : BUFG    port map ( I => clk40_90_pre_buf, O => clk40_90_i );
  --  bufg_clk40inv  : BUFG    port map ( I => clk40_180_pre_buf, O => clk40_180_i );
  bufg_clk80     : BUFG    port map ( I => clk80_pre_buf, O => clk80_i );
--  bufg_clk80_180 : BUFG    port map ( I => clk80_180_pre_buf, O => clk80_180_i );

end default;