library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity clkbuf_lvds is
  port(
    PADP   :  in    STD_ULOGIC;
    PADN   :  in    STD_ULOGIC;
    Y      :  out   STD_ULOGIC);
end clkbuf_lvds;

architecture default of clkbuf_lvds is

begin

  sys_clk_inbuf  : IBUFGDS port map ( I => PADP, IB => PADN, O => Y );

end default;