library ieee;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;

entity tp_sram is
generic (use_dp : boolean  := true;
         Na     : positive :=  7;
         Nd     : positive := 64);
port(
    clk     : in  std_logic;
    we      : in  std_logic;
    addrA   : in  std_logic_vector(Na-1 downto 0);
    addrB   : in  std_logic_vector(Na-1 downto 0);
    dinA    : in  std_logic_vector(Nd-1 downto 0);
    doutA   : out std_logic_vector(Nd-1 downto 0);
    doutB   : out std_logic_vector(Nd-1 downto 0) );
end tp_sram;

architecture a of tp_sram is

component dp_sram is
generic (Na     : Positive := 7;
         Nd     : positive := 64);
port(
    clk     : in  std_logic;
    we      : in  std_logic;
    waddr   : in  std_logic_vector(Na-1 downto 0);
    raddr   : in  std_logic_vector(Na-1 downto 0);
    din     : in  std_logic_vector(Nd-1 downto 0);
    dout    : out std_logic_vector(Nd-1 downto 0) );
end component;

type t_mem_data is array(0 to 2**addrA'length - 1) of std_logic_vector(doutA'range);
signal mem_data  : t_mem_data;

signal raddrAi   : integer range 0 to 2**addrA'length - 1;
signal raddrBi   : integer range 0 to 2**addrB'length - 1;

signal addrAi    : integer range 0 to 2**addrA'length - 1;
signal addrBi    : integer range 0 to 2**addrA'length - 1;

begin
     addrAi <= conv_integer(addrA);
     addrBi <= conv_integer(addrB);

tport: if use_dp = false generate
ram: process(clk)
    begin
        if clk'event and clk='1' then
            raddrAi <= addrAi;
            raddrBi <= addrBi;
            if we = '1' then
                mem_data(addrAi) <= dinA;
            end if;
        end if;
    end process;

    doutA <= mem_data(raddrAi) after 5 ns;
    doutB <= mem_data(raddrBi) after 5 ns;

end generate;

dport: if use_dp = true generate

dp1: dp_sram
generic map(Na => Na,
            Nd => Nd)
port map(
    clk     => clk,
    we      => we,
    waddr   => addrA,
    raddr   => addrA,
    din     => dinA,
    dout    => doutA);

dp2: dp_sram
generic map(Na => Na,
            Nd => Nd)
port map(
    clk     => clk,
    we      => we,
    waddr   => addrA,
    raddr   => addrB,
    din     => dinA,
    dout    => doutB);

end generate;

end;