-- $Id$: library ieee; USE IEEE.std_logic_1164.ALL; library proasic3e; use proasic3e.all; entity ram4k9_actel is generic (piperA : boolean := false; -- pipelined read piperB : boolean := false; -- pipelined read Na_A : Positive := 9; -- 9, 9, 10, 11, 12 address width Nd_A : Positive := 9; -- 9, 8, 4, 2, 1 data width Na_B : Positive := 12; -- 9, 9, 10, 11, 12 address width Nd_B : positive := 1); -- 9, 8, 4, 2, 1 data width port( clkA : in std_logic; clkB : in std_logic; weA : in std_logic; weB : in std_logic; addrA : in std_logic_vector(Na_A-1 downto 0); addrB : in std_logic_vector(Na_B-1 downto 0); dinA : in std_logic_vector(Nd_A-1 downto 0); dinB : in std_logic_vector(Nd_B-1 downto 0); doutA : out std_logic_vector(Nd_A-1 downto 0); doutB : out std_logic_vector(Nd_B-1 downto 0) ); end ram4k9_actel; architecture a of ram4k9_actel is COMPONENT ram4k9 generic( MEMORYFILE : String := ""); port( ADDRA0 : in STD_ULOGIC; ADDRA1 : in STD_ULOGIC; ADDRA2 : in STD_ULOGIC; ADDRA3 : in STD_ULOGIC; ADDRA4 : in STD_ULOGIC; ADDRA5 : in STD_ULOGIC; ADDRA6 : in STD_ULOGIC; ADDRA7 : in STD_ULOGIC; ADDRA8 : in STD_ULOGIC; ADDRA9 : in STD_ULOGIC; ADDRA10 : in STD_ULOGIC; ADDRA11 : in STD_ULOGIC; DINA0 : in STD_ULOGIC; DINA1 : in STD_ULOGIC; DINA2 : in STD_ULOGIC; DINA3 : in STD_ULOGIC; DINA4 : in STD_ULOGIC; DINA5 : in STD_ULOGIC; DINA6 : in STD_ULOGIC; DINA7 : in STD_ULOGIC; DINA8 : in STD_ULOGIC; WIDTHA0 : in STD_ULOGIC; WIDTHA1 : in STD_ULOGIC; PIPEA : in STD_ULOGIC; WMODEA : in STD_ULOGIC; BLKA : in STD_ULOGIC; WENA : in STD_ULOGIC; CLKA : in STD_ULOGIC; ADDRB0 : in STD_ULOGIC; ADDRB1 : in STD_ULOGIC; ADDRB2 : in STD_ULOGIC; ADDRB3 : in STD_ULOGIC; ADDRB4 : in STD_ULOGIC; ADDRB5 : in STD_ULOGIC; ADDRB6 : in STD_ULOGIC; ADDRB7 : in STD_ULOGIC; ADDRB8 : in STD_ULOGIC; ADDRB9 : in STD_ULOGIC; ADDRB10 : in STD_ULOGIC; ADDRB11 : in STD_ULOGIC; DINB0 : in STD_ULOGIC; DINB1 : in STD_ULOGIC; DINB2 : in STD_ULOGIC; DINB3 : in STD_ULOGIC; DINB4 : in STD_ULOGIC; DINB5 : in STD_ULOGIC; DINB6 : in STD_ULOGIC; DINB7 : in STD_ULOGIC; DINB8 : in STD_ULOGIC; WIDTHB0 : in STD_ULOGIC; WIDTHB1 : in STD_ULOGIC; PIPEB : in STD_ULOGIC; WMODEB : in STD_ULOGIC; BLKB : in STD_ULOGIC; WENB : in STD_ULOGIC; CLKB : in STD_ULOGIC; RESET : in STD_ULOGIC; DOUTA0 : out STD_ULOGIC; DOUTA1 : out STD_ULOGIC; DOUTA2 : out STD_ULOGIC; DOUTA3 : out STD_ULOGIC; DOUTA4 : out STD_ULOGIC; DOUTA5 : out STD_ULOGIC; DOUTA6 : out STD_ULOGIC; DOUTA7 : out STD_ULOGIC; DOUTA8 : out STD_ULOGIC; DOUTB0 : out STD_ULOGIC; DOUTB1 : out STD_ULOGIC; DOUTB2 : out STD_ULOGIC; DOUTB3 : out STD_ULOGIC; DOUTB4 : out STD_ULOGIC; DOUTB5 : out STD_ULOGIC; DOUTB6 : out STD_ULOGIC; DOUTB7 : out STD_ULOGIC; DOUTB8 : out STD_ULOGIC); END COMPONENT; signal WIDTHA : std_logic_vector(1 downto 0); signal WIDTHB : std_logic_vector(1 downto 0); signal WENA : std_logic; signal WENB : std_logic; signal BLKA : std_logic; signal BLKB : std_logic; signal WMODEA : std_logic; signal WMODEB : std_logic; signal PIPEA : std_logic; signal PIPEB : std_logic; signal RESET : std_logic; signal AD_A : std_logic_vector(11 downto 0); signal AD_B : std_logic_vector(11 downto 0); signal DI_A : std_logic_vector( 8 downto 0); signal DI_B : std_logic_vector( 8 downto 0); signal DO_A : std_logic_vector( 8 downto 0); signal DO_B : std_logic_vector( 8 downto 0); begin RESET <= '1'; -- don't use it now PIPEA <= '1' when piperA else '0'; -- pipelined read PIPEB <= '1' when piperB else '0'; -- pipelined read WENA <= not weA; WENB <= not weB; BLKA <= '0'; -- always read BLKB <= '0'; -- always read WMODEA <= '0'; -- 0 - last read, 1 - pass through WMODEB <= '0'; -- 0 - last read, 1 - pass through process(addrA, addrB, dinA, dinB, DO_A, DO_B) begin AD_A <= (others => '0'); -- fill the upper bits with 0 AD_A(addrA'range) <= addrA; AD_B <= (others => '0'); -- fill the upper bits with 0 AD_B(addrB'range) <= addrB; -- write data DI_A <= (others => '0'); -- fill the upper bits with 0 DI_A(dinA'range) <= dinA; DI_B <= (others => '0'); -- fill the upper bits with 0 DI_B(dinB'range) <= dinB; -- read data doutA <= DO_A(doutA'range); doutB <= DO_B(doutB'range); end process; WIDTHA <= "00" when Na_A = 12 and Nd_A = 1 else "01" when Na_A = 11 and Nd_A = 2 else "10" when Na_A = 10 and Nd_A = 4 else "11" when Na_A = 9 and ((Nd_A = 8) or (Nd_A = 9)) else "XX"; WIDTHB <= "00" when Na_B = 12 and Nd_B = 1 else "01" when Na_B = 11 and Nd_B = 2 else "10" when Na_B = 10 and Nd_B = 4 else "11" when Na_B = 9 and ((Nd_B = 8) or (Nd_B = 9)) else "XX"; ram: ram4k9 -- generic( -- MEMORYFILE : String := ""); port map( ADDRA0 => AD_A(0), ADDRA1 => AD_A(1), ADDRA2 => AD_A(2), ADDRA3 => AD_A(3), ADDRA4 => AD_A(4), ADDRA5 => AD_A(5), ADDRA6 => AD_A(6), ADDRA7 => AD_A(7), ADDRA8 => AD_A(8), ADDRA9 => AD_A(9), ADDRA10 => AD_A(10), ADDRA11 => AD_A(11), DINA0 => DI_A(0), DINA1 => DI_A(1), DINA2 => DI_A(2), DINA3 => DI_A(3), DINA4 => DI_A(4), DINA5 => DI_A(5), DINA6 => DI_A(6), DINA7 => DI_A(7), DINA8 => DI_A(8), WIDTHA0 => WIDTHA(0), WIDTHA1 => WIDTHA(1), PIPEA => PIPEA, WMODEA => WMODEA, BLKA => BLKA, WENA => WENA, CLKA => CLKA, ADDRB0 => AD_B(0), ADDRB1 => AD_B(1), ADDRB2 => AD_B(2), ADDRB3 => AD_B(3), ADDRB4 => AD_B(4), ADDRB5 => AD_B(5), ADDRB6 => AD_B(6), ADDRB7 => AD_B(7), ADDRB8 => AD_B(8), ADDRB9 => AD_B(9), ADDRB10 => AD_B(10), ADDRB11 => AD_B(11), DINB0 => DI_B(0), DINB1 => DI_B(1), DINB2 => DI_B(2), DINB3 => DI_B(3), DINB4 => DI_B(4), DINB5 => DI_B(5), DINB6 => DI_B(6), DINB7 => DI_B(7), DINB8 => DI_B(8), WIDTHB0 => WIDTHB(0), WIDTHB1 => WIDTHB(1), PIPEB => PIPEB, WMODEB => WMODEB, BLKB => BLKB, WENB => WENB, CLKB => CLKB, RESET => RESET, DOUTA0 => DO_A(0), DOUTA1 => DO_A(1), DOUTA2 => DO_A(2), DOUTA3 => DO_A(3), DOUTA4 => DO_A(4), DOUTA5 => DO_A(5), DOUTA6 => DO_A(6), DOUTA7 => DO_A(7), DOUTA8 => DO_A(8), DOUTB0 => DO_B(0), DOUTB1 => DO_B(1), DOUTB2 => DO_B(2), DOUTB3 => DO_B(3), DOUTB4 => DO_B(4), DOUTB5 => DO_B(5), DOUTB6 => DO_B(6), DOUTB7 => DO_B(7), DOUTB8 => DO_B(8)); end;