library ieee;
use ieee.std_logic_1164.all;

entity obuf is
port ( I : in  std_logic;
       O : out std_logic);
end obuf;

architecture a of obuf is

COMPONENT OUTBUF
    port(
            D   : in  STD_ULOGIC;
            PAD : out STD_ULOGIC);
END COMPONENT;

begin

ob: outbuf port map(d => I, pad => O);

end;