library ieee;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;

entity dp_sram is
generic (Na     : Positive := 7;
         Nd     : positive := 64);
port(
    clk     : in  std_logic;
    we      : in  std_logic;
    waddr   : in  std_logic_vector(Na-1 downto 0);
    raddr   : in  std_logic_vector(Na-1 downto 0);
    din     : in  std_logic_vector(Nd-1 downto 0);
    dout    : out std_logic_vector(Nd-1 downto 0) );
end dp_sram;

architecture a of dp_sram is

type t_mem_data is array(0 to 2**waddr'length - 1) of std_logic_vector(dout'range);
signal mem_data : t_mem_data;
signal raddri   : integer range 0 to 2**raddr'length - 1;
signal waddri   : integer range 0 to 2**waddr'length - 1;

signal we_old   : std_logic;
signal din_old  : std_logic_vector(din'range);

begin
     waddri <= conv_integer(waddr);

ram: process(clk)
    begin
        if clk'event and clk='1' then
            raddri <= conv_integer(raddr);
            we_old <= we;
            din_old <= din;
            if we_old = '1' then
                mem_data(raddri) <= din_old;
            end if;
        end if;
    end process;

    dout <= mem_data(raddri) after 5 ns;
end;