###############################################################################
# Device, package & speed grade
###############################################################################
CONFIG PART = XC3S500E-4PQ208;

###############################################################################
# Clock constraints
###############################################################################
NET "clock_generation/clk40_pre_dcm" TNM_NET = "TNM_clk_40";
TIMESPEC "TS_clk_40" = PERIOD "TNM_clk_40" 42 Mhz INPUT_JITTER 200 ps;

###############################################################################
# I/O
###############################################################################

##### DCS board #####
NET "CLK120n"  LOC = "P184"  | IOSTANDARD = LVDS_25;
NET "CLK120p"  LOC = "P183"  | IOSTANDARD = LVDS_25;
NET "CLK40n" LOC = "P186" | IOSTANDARD = LVDS_25;
NET "CLK40p" LOC = "P185" | IOSTANDARD = LVDS_25;
NET "SCSNFEBINn"  LOC = "P197" | IOSTANDARD = LVDS_25 ;
NET "SCSNFEBINp"  LOC = "P196" | IOSTANDARD = LVDS_25 ;
NET "SCSNFEBOUTn"  LOC = "P200" | IOSTANDARD = LVDS_25 ;
NET "SCSNFEBOUTp"  LOC = "P199" | IOSTANDARD = LVDS_25 ;
NET "SCSNINn"  LOC = "P203"  | IOSTANDARD = LVDS_25;
NET "SCSNINp"  LOC = "P202"  | IOSTANDARD = LVDS_25;
NET "SCSNOUTn"  LOC = "P206"  | IOSTANDARD = LVDS_25;
NET "SCSNOUTp"  LOC = "P205"  | IOSTANDARD = LVDS_25;
NET "L1ACCEPTn"  LOC = "P193" | IOSTANDARD = LVDS_25 ;
NET "L1ACCEPTp"  LOC = "P192" | IOSTANDARD = LVDS_25 ;

##### TLMU #####
NET "CNRRL" LOC = "P25" | IOSTANDARD = LVTTL;
NET "RESET_TOFFPGA" LOC="P31" | IOSTANDARD = LVTTL;
NET "CLK40T" LOC = "P48" | IOSTANDARD = LVTTL; # clock output for TOF Fpga

NET "TLMU_trg<0>"  LOC = "P65" | IOSTANDARD = LVTTL ;
NET "TLMU_trg<1>"  LOC = "P64" | IOSTANDARD = LVTTL ;
NET "TLMU_trg<2>"  LOC = "P63" | IOSTANDARD = LVTTL ;
NET "TLMU_trg<3>"  LOC = "P62" | IOSTANDARD = LVTTL ;
NET "TLMU_trg<4>"  LOC = "P61" | IOSTANDARD = LVTTL ;
NET "TLMU_trg<5>"  LOC = "P60" | IOSTANDARD = LVTTL ;
NET "TLMU_trg<6>"  LOC = "P56" | IOSTANDARD = LVTTL ;
NET "TLMU_trg<7>"  LOC = "P55" | IOSTANDARD = LVTTL ;

NET "IF17x_SCSN_IN"  LOC = "P74" | IOSTANDARD = LVTTL ;
NET "IF17x_SCSN_OUT"  LOC = "P75" | IOSTANDARD = LVTTL;

##### PIM #####
NET "PIMLINK<0>"  LOC = "P23" | IOSTANDARD = LVTTL ;
NET "PIMLINK<1>"  LOC = "P33" | IOSTANDARD = LVTTL;
NET "PIMLINK<2>"  LOC = "P42" | IOSTANDARD = LVTTL;

##### TTCex #####
INST "a_channel_out" IOB = TRUE; 
INST "b_channel_out" IOB = TRUE;
NET "A_ECL"  LOC = "P8" | IOSTANDARD = LVTTL ;
NET "B_Channel"  LOC = "P50" | IOSTANDARD = LVTTL;
NET "B_ECL"  LOC = "P12" | IOSTANDARD = LVTTL;
NET "BC_ECL"  LOC = "P18" | IOSTANDARD = LVTTL ;
NET "A_ECL" OFFSET = OUT AFTER "CLK40n";
NET "B_ECL" OFFSET = OUT AFTER "CLK40n"; 
NET "BC_ECL" OFFSET = OUT AFTER "CLK40n";

##### GTU #####
NET "BUSY"  LOC = "P96" | IOSTANDARD = LVTTL; # adjacent to CB_A

##### CB-A/C #####
NET "CB_A"  LOC = "P97" | IOSTANDARD = LVTTL;
INST "ibuf_cba" IOB = FALSE; # register not in IOB in order to use IDDR for BUSY (adjacent cell)
NET "CB_C"  LOC = "P99" | IOSTANDARD = LVTTL ;

##### Miscellaneous #####
NET "LED1"  LOC = "P102" | IOSTANDARD = LVTTL ;
NET "LED2"  LOC = "P103" | IOSTANDARD = LVTTL ;

NET "SPA"  LOC = "P35" | IOSTANDARD = LVTTL;
NET "SPB"  LOC = "P41" | IOSTANDARD = LVTTL;
NET "S1_IN1"  LOC = "P2" | IOSTANDARD = LVTTL ;
NET "S1_OUT1"  LOC = "P11" | IOSTANDARD = LVTTL;
NET "S1_OUT2"  LOC = "P15" | IOSTANDARD = LVTTL;
NET "S2_OUT1"  LOC = "P16" | IOSTANDARD = LVTTL;
NET "S2_OUT2"  LOC = "P19" | IOSTANDARD = LVTTL;