library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library unisim;
use unisim.vcomponents.all;

entity trg_lut is
  port (
    clk40  : in std_logic;
    rst40  : in std_logic;

    tlmu_in : in std_logic_vector(7 downto 0);
    cbc_in  : in std_logic_vector(1 downto 0);
    cba_in  : in std_logic_vector(1 downto 0);
    bc_in   : in std_logic;
    
    pattern_tof : in std_logic_vector(4 downto 0);  
    pattern_cba : in std_logic_vector(1 downto 0); 
    pattern_cbc : in std_logic_vector(1 downto 0); 
    pattern_match_tof : out std_logic;
    pattern_match_cba : out std_logic;
    pattern_match_cbc : out std_logic;

    lut_mon : out std_logic_vector(12 downto 0);

    trigger : out std_logic_vector(1 downto 0);

    scsn_addr : in std_logic_vector(15 downto 0);
    scsn_din  : in std_logic_vector(31 downto 0);
    scsn_we   : in std_logic;
    scsn_req  : in std_logic;
    scsn_dout : out std_logic_vector(31 downto 0);
    scsn_ack  : out std_logic
  );
end trg_lut;


architecture default of trg_lut is

  signal trigger_i : std_logic_vector(1 downto 0);

  signal ctb_cba : std_logic_vector(1 downto 0);
  signal ctb_cbc : std_logic_vector(1 downto 0);
  signal ctb_tof : std_logic_vector(4 downto 0);

  signal scsn_rd : std_logic;
  
begin

  --
  -- I/O mapping
  trigger <= trigger_i;
  
  process (clk40)
  begin
    if rst40 = '1' then
      lut_mon <= (others => '0');
    elsif rising_edge(clk40) then
      lut_mon <= bc_in & tlmu_in(7 downto 0) & cbc_in & cba_in;
    end if;
  end process;

  bram_lut_inst : RAMB16_S2_S36
    generic map (
      WRITE_MODE_A => "READ_FIRST",
      WRITE_MODE_B => "READ_FIRST"
    )
    port map (
      -- port A : reading using BC
      ADDRA( 1 downto 0) => cba_in,
      ADDRA( 3 downto 2) => cbc_in,
      ADDRA(11 downto 4) => tlmu_in,
      ADDRA(12)  => bc_in,
      DIA   => (others => '1'),
      DOA   => trigger_i,
      WEA   => '0',
      ENA   => '1',
      SSRA  => rst40, 
      CLKA  => clk40,

      -- port B : read/write via SCSN
      ADDRB => scsn_addr(8 downto 0),
      DIB   => scsn_din,
      DIPB  => (others => '1'),
      DOB   => scsn_dout,
      DOPB  => open,
      WEB   => scsn_we,
      ENB   => '1',
      SSRB  => rst40, 
      CLKB  => clk40
    );

  process (clk40)
  begin
    if rst40 = '1' then
      scsn_rd <= '0';
    elsif rising_edge(clk40) then
      if scsn_req = '1' then
        scsn_rd <= '1';
      else
        scsn_rd <= '0';
      end if;
    end if;
  end process;

  process (clk40)
  begin
    if rst40 = '1' then
      scsn_ack <= '0';
    elsif rising_edge(clk40) then
      if scsn_req = '1' then
        scsn_ack <= '1';
      else
        scsn_ack <= '0';
      end if;
    end if;
  end process;
  
  cmp_pattern : process (clk40)
  begin
    if rst40 = '1' then
      pattern_match_tof <= '0';
      pattern_match_cba <= '0';
      pattern_match_cbc <= '0';
    elsif rising_edge(clk40) then
      if cba_in = pattern_cba then
        pattern_match_cba <= '1';
      else
        pattern_match_cba <= '0';
      end if;

      if cbc_in = pattern_cbc then
        pattern_match_cbc <= '1';
      else
        pattern_match_cbc <= '0';
      end if;

      if tlmu_in = pattern_tof then
        pattern_match_tof <= '1';
      else
        pattern_match_tof <= '0';
      end if;
    end if;
  end process;

end default;