library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity random_pulser is
  port (
    clk40 : in std_logic;
    rst40 : in std_logic;

    thr : in std_logic_vector(31 downto 0);

    pulse : out std_logic
  );
end random_pulser;

architecture default of random_pulser is

  signal rnd : std_logic_vector(31 downto 0);

  signal rnd_valid : std_logic;

begin

  rng : entity work.mersenne_twister
    port map (
      clk40 => clk40,
      rst40 => rst40,
      rnd   => rnd,
      valid => rnd_valid
    );
  
  process (clk40)
  begin
    if rst40 = '1' then
      pulse <= '0';
    elsif rising_edge(clk40) and rnd_valid = '1' then
      if (rnd <= thr) then
        pulse <= '1';
      else
        pulse <= '0';
      end if;
    end if;
  end process;
  
end default;