library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;

entity cb_ac_sample is
  
  port (
    clk40: in std_logic;
    rst40: in std_logic;
    clk_s : in std_logic;
    rst_s : in std_logic;

    cb_sample_par: in std_logic_vector(1 downto 0);
    cb_in: in std_logic;
    cb_out: out std_logic_vector(1 downto 0)
  );

end cb_ac_sample;

architecture oversample160 of cb_ac_sample is

  signal cb_par    : std_logic_vector(5 downto 0);
  signal cb_par_r  : std_logic_vector(5 downto 0);


  begin

  process (clk_s)
  begin
    if rst_s = '1' then
      cb_par <= (others => '0');
    elsif rising_edge(clk_s) then
      cb_par(0) <= cb_in;
      cb_par : for i in 1 to 5 loop
        cb_par(i) <= cb_par(i-1);
      end loop;
    end if;
  end process;

  process (clk40)
  begin
    if rst40 = '1' then
      cb_par_r  <= (others => '0');
    elsif rising_edge(clk40) then
      cb_par_r <= cb_par;
    end if;
  end process;
  
  with cb_sample_par select
      cb_out <= cb_par_r(5) & cb_par_r(3) when "00",
                cb_par_r(3) & cb_par_r(1) when "01",
                cb_par_r(4) & cb_par_r(2) when "10",
                cb_par_r(2) & cb_par_r(0) when "11",
                cb_par_r(5) & cb_par_r(3) when others;

  end oversample160;