library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;

entity bc_trigger is
  port (
    clk40 : in std_logic;
    rst40 : in std_logic;

    clk_scsn : in std_logic;
    rst_scsn : in std_logic;

    scsn_addr : in std_logic_vector(15 downto 0);
    scsn_din  : in std_logic_vector(31 downto 0);
    scsn_dout : out std_logic_vector(31 downto 0);
    scsn_we   : in std_logic;
    scsn_req  : in std_logic;
    scsn_ack  : out std_logic;

    bc : in std_logic_vector(11 downto 0);

    trg : out std_logic
  );
end bc_trigger;

architecture default of bc_trigger is

  signal trg_ctb : std_logic_vector(0 downto 0);

  signal scsn_req_r : std_logic;

  signal we : std_logic;

begin

  --
  -- output mapping
  trg <= trg_ctb(0);
  
  we <= scsn_we when (scsn_addr(11 downto 9) = "000") else '0';

  process (clk40)
  begin
    if rst40 = '1' then
      scsn_req_r <= '0';
      scsn_ack   <= '0';
    elsif rising_edge(clk40) then
      scsn_req_r <= scsn_req;
      scsn_ack   <= scsn_req_r;
    end if;
  end process;

  bram_inst : RAMB16_S1_S36
    generic map (
      WRITE_MODE_A => "READ_FIRST",
      WRITE_MODE_B => "READ_FIRST"
--      INIT_00 => x"00000000_00000000_00000000_00000000_00000000_00000D00_00800000_00000100"
    )
    port map (
      -- port A : reading using BC
      ADDRA(13 downto 12) => "00",
      ADDRA(11 downto 0) => bc,
      DIA   => (others => '1'),
      DOA   => trg_ctb,
      WEA   => '0',
      ENA   => '1',
      SSRA  => rst40, 
      CLKA  => clk40,
    
      -- port B : writing via SCSN
      ADDRB => scsn_addr(8 downto 0),
      DIB   => scsn_din,
      DIPB  => (others => '1'),
      DOB   => scsn_dout,
      DOPB  => open,
      WEB   => we,
      ENB   => '1',
      SSRB  => rst_scsn, 
      CLKB  => clk_scsn
    );
end default;