library IEEE;
use IEEE.std_logic_1164.all;

entity trg_emulator_tb is 

end trg_emulator_tb;    

architecture default of trg_emulator_tb is

  constant clk40_period : time := 25 ns;

  signal clk40 : std_logic;
  signal rst40 : std_logic;

  signal pretrigger : std_logic;
  signal l0 : std_logic;
  signal l1 : std_logic;
  
  signal pt_out : std_logic;
  signal l0_out : std_logic;
  signal l1_out : std_logic;

begin  -- default

  -- clock generation
  process
  begin
    clk40 <= '1';
    wait for clk40_period / 2;
    clk40 <= '0';
    wait for clk40_period / 2;
  end process;

  process
  begin
    wait for clk40_period/2;
    rst40 <= '1';
    wait for 2*clk40_period;
    rst40 <= '0';
    wait;
  end process;

  process
  begin
    pretrigger <= '0';
    l0 <= '0';
    l1 <= '0';
    wait for 10.0 * clk40_period;
    pretrigger <= '0';
    wait for clk40_period;
    pretrigger <= '0';
    wait for 10.0*clk40_period;
    l0 <= '1';
    wait for clk40_period;
    l0 <= '0';
    wait for 30 * clk40_period;
    l1 <= '1';
    wait for clk40_period;
    l1 <= '0';
    wait for 10 us;
    wait for 10.0 * clk40_period;
    pretrigger <= '1';
    wait for clk40_period;
    pretrigger <= '0';
    wait for 10.0*clk40_period;
    l0 <= '1';
    wait for clk40_period;
    l0 <= '0';
    wait for 30 * clk40_period;
    l1 <= '1';
    wait for clk40_period;
    l1 <= '0';
    wait for 10 us;
  end process;

  -- instantiation of dut
  dut_trg_generator : entity work.trg_emulator port map (
    clk40 => clk40,
    rst40 => rst40,

    pt_in => pretrigger,
    l0_in => l0,
    l1_in => l1,

    pt_out => pt_out,
    l0_out => l0_out,
    l1_out => l1_out
  );


end default;