library ieee;
use ieee.std_logic_1164.all;

entity timing_analyzer_tb is

end timing_analyzer_tb;

architecture default of timing_analyzer_tb is

  constant clk40_period : time := 25 ns;

  signal clk40  : std_logic;
  signal rst40  : std_logic;
  signal clk120 : std_logic;
  signal rst120 : std_logic;

  signal signals : std_logic_vector(31 downto 0);

  signal arm : std_logic;
  
begin
  process
  begin
    clk40 <= '1';
    wait for clk40_period/2;
    clk40 <= '0';
    wait for clk40_period/2;
  end process;
  
  process
  begin
    rst40 <= '1';
    wait for 10*clk40_period;
    rst40 <= '0';
    wait;
  end process;

  process
  begin
    clk120 <= '1';
    wait for clk40_period/3/2;
    clk120 <= '1';
    wait for clk40_period/3/2;
  end process;
  
  process
  begin
    rst120 <= '1';
    wait for 10*clk40_period;
    rst120 <= '0';
    wait;
  end process;

  -- some signals
  process
  begin
    signals <= (others => '0');
    wait for 120*clk40_period;
    signals <= x"00000001";
    wait for 5*clk40_period;
    signals <= x"00000002";
    wait for 5*clk40_period;
    signals <= x"00000003";
    wait for 5*clk40_period;
    signals <= x"00000004";
    wait;
  end process;

  -- arming
  process
  begin
    arm <= '0';
    wait for 14*clk40_period;
    arm <= '1';
    wait for clk40_period;
    arm <= '0';
    wait for 600*clk40_period;
    arm <= '1';
    wait for clk40_period;
    arm <= '0';
    wait;
  end process;

  tim_ana : entity work.timing_analyzer
    port map (
      clk40 => clk40,
      rst40 => rst40,

      clk120 => clk120,
      rst120 => rst120,

      signals => signals,
      trg_mask => x"00000002",
      arm => arm,
      
      scsn_addr => (others => '0'),
      scsn_data => open,
      scsn_req  => '0',
      scsn_ack  => open
    );

end default;