library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use std.textio.all;

entity mt_tb is

end mt_tb;

architecture default of mt_tb is

  constant clk40_period : time := 25 ns;

  signal clk40 : std_logic;
  signal rst40 : std_logic;
  signal rnd   : std_logic_vector(31 downto 0);
  
  file rndfile : text open write_mode is "rnd.dat";

begin

  process
    variable log : line;
    variable i : integer := 0;
  begin
    clk40 <= '1';
    wait for clk40_period/2;
    if (i >= 19) then
      write(log, i-19);
      write(log, " ");
      hwrite(log, rnd);
      writeline(rndfile, log);
    end if;
    i := i+1;
    clk40 <= '0';
    wait for clk40_period/2;
  end process;

  process
  begin
    rst40 <= '1';
    wait for 10*clk40_period+clk40_period/2;
    rst40 <= '0';
    wait;
  end process;
  
  mt : entity work.mersenne_twister
    port map (
      clk40 => clk40,
      rst40 => rst40,
      rnd   => rnd
    );

end default;