library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity ctp_tin_tb is end ctp_tin_tb; architecture default of ctp_tin_tb is signal clk40_period : time := 25 ns; signal clk40 : std_logic; signal rst40 : std_logic; signal trg : std_logic; signal rnd_pulse : std_logic; signal rnd_thr : std_logic_vector(31 downto 0) := x"02000000"; begin process begin clk40 <= '1'; wait for clk40_period/2; clk40 <= '0'; wait for clk40_period/2; end process; process begin rst40 <= '1'; wait for 10*clk40_period; rst40 <= '0'; wait; end process; rnd_trg : entity work.random_pulser port map ( clk40 => clk40, rst40 => rst40, thr => rnd_thr, pulse => rnd_pulse ); ctp_tin_inst : entity work.ctp_tin generic map ( signature => conv_std_logic_vector(83, 7) ) port map ( clk40 => clk40, rst40 => rst40, opt_code => "01", trg_ctb => rnd_pulse, rnd_trg => rnd_pulse, trg_out => trg ); end default;