library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity bc_trg_tb is

end bc_trg_tb;

architecture default of bc_trg_tb is

  signal clk40_period : time := 25 ns;

  signal clk40 : std_logic;
  signal rst40 : std_logic;

  signal trg : std_logic;

  signal rst_bunch_counter_ttcrx : std_logic := '0';
  signal bc : unsigned(11 downto 0);
  signal bc_rst_val : unsigned(11 downto 0) := to_unsigned(53, 12);
  signal bc_max_val : unsigned(11 downto 0) := to_unsigned(3563, 12);
  signal bc_offset : signed(12 downto 0);

  signal rnd_pulse : std_logic;

  signal rnd_thr : unsigned(31 downto 0) := x"02000000";

begin

  process
  begin
    clk40 <= '1';
    wait for clk40_period/2;
    clk40 <= '0';
    wait for clk40_period/2;
  end process;

  process
  begin
    rst40 <= '1';
    wait for 10*clk40_period;
    rst40 <= '0';
    wait;
  end process;

  rnd_trg : entity work.random_pulser
    port map (
      clk40 => clk40,
      rst40 => rst40,

      thr => std_logic_vector(rnd_thr),

      pulse => rnd_pulse
    );

  ctp_tin_inst : entity work.ctp_tin
    generic map (
      signature => std_logic_vector(to_unsigned(83, 7))
    )
    port map (
      clk40 => clk40,
      rst40 => rst40,

      opt_code => "01",

      trg_ctb => rnd_pulse,
      rnd_trg => rnd_pulse,

      trg_out => open
    );

  process (clk40)
  begin
    if rst40 = '1' then
      bc <= (others => '0');
      bc_offset <= (others => '0');
    elsif rising_edge(clk40) then
      if rst_bunch_counter_ttcrx = '1' then
        bc <= bc_rst_val;
      elsif bc = bc_max_val then
        bc <= (others => '0');
      else
        bc <= bc + 1;
      end if;
      
      bc_offset <= signed('0' & bc) - signed('0' & bc_rst_val);

      -- capture BC at L0
--      if l0_ttcrx = '1' then
--        bc_l0 <= bc;
--      end if;

      -- determine offset in BC w.r.t. the one sent by CTP
--      if l2m_ttcrx = '1' then
--        bc_offset <= bc_l0 - l2a_message_ttcrx(11 downto 0);
--      end if;
    end if;
  end process;


  bc_trg_inst : entity work.bc_trigger
    port map (
      clk40 => clk40,
      rst40 => rst40,

      scsn_addr => (others => '0'),
      scsn_data => (others => '0'),
      scsn_we   => '0',

      bc => std_logic_vector(bc),

      trg => trg
    );

end default;