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-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:14:25 04/04/2008 
-- Design Name: 
-- Module Name:    falling_edge_sync - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity falling_edge_sync is
    Port ( signal_in : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           edge_detected : out  STD_LOGIC);
end falling_edge_sync;

architecture Behavioral of falling_edge_sync is

signal sig1 : std_logic;
signal sig2 : std_logic := '0';
signal sig3, sig4 : std_logic;
signal sig5, sig6 : std_logic;
signal sig7, sig8 : std_logic;

begin
   -- make sure that the deadtime is as low as possible
	-- if two edge detections are used in parallel with a mux for no deadtime,
	-- then this garanties that if a puls came in the deadtime of one rising
	-- edge detector and now the puls is recognized by the other. 
	-- TODO But avoid that one puls is detected twice. By fake edges caused by Mux
	-- switching. Solution use clock enable of the input edge detection registers.
	sig8 <= sig3 and clk;
   -- first edge detection and trap register
	process(signal_in, sig8)
	begin
	   if sig8 = '1' then
		   sig5 <= '0';
		elsif signal_in'event and signal_in = '0' then
         sig5 <= '1';
		end if;
	end process;
	-- make sure setup times are kept only change at a high clock
	sig4 <= clk and sig5;
	
	-- make sure that the hold time is valid; hold time of 0ns is ok 
	-- according to the datasheet; but this is achived by a place and route trick
	-- in the FPGA; since this circuit is so freaky the tool cannot do it so this
	-- is neccessary
	sig7 <= sig3 and not clk;
   -- second edge detection and trap register after setup condition
	process(sig4, sig7)
	begin
	   if sig7 = '1' then
		   sig2 <= '0';
	   elsif sig4'event and sig4 = '1' then
		   sig2 <= '1';
		end if;
	end process;
	sig1 <= not sig2;
	

   -- register to shape puls to one cycle
	process(sig2, clk)
	begin
	   if clk'event and clk = '1' then
	      sig3 <= sig2;
      end if;			
	end process;
	
	edge_detected <= sig2;

end Behavioral;