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-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:10:34 04/04/2008 
-- Design Name: 
-- Module Name:    delay_and_sync - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity delay_and_sync is
    Port ( signal_in : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           set_delay : in  STD_LOGIC_VECTOR (4 downto 0);
			  reset: in STD_LOGIC;
           signal_sync_delayed_0 : out  STD_LOGIC;
			  signal_sync_delayed_1 : out  STD_LOGIC;
			  signal_sync_delayed_2 : out  STD_LOGIC;
			  signal_sync_delayed_3 : out  STD_LOGIC);
end delay_and_sync;

architecture Behavioral of delay_and_sync is

	COMPONENT falling_edge_sync
	PORT(
		signal_in : IN std_logic;
		clk : IN std_logic;          
		edge_detected : OUT std_logic
		);
	END COMPONENT;

	COMPONENT rising_edge_sync
	PORT(
		signal_in : IN std_logic;
		clk : IN std_logic;          
		edge_detected : OUT std_logic
		);
	END COMPONENT;

   component Mux32_bit
	   port (
	   M: IN std_logic_VECTOR(31 downto 0);
	   S: IN std_logic_VECTOR(4 downto 0);
	   O: OUT std_logic);
   end component;

   -- Synplicity black box declaration
	attribute syn_black_box : boolean;
   attribute syn_black_box of Mux32_bit: component is true;
	
   signal sig1: std_logic_vector(1 downto 0);
	signal sig2: std_logic;
	signal sig3: std_logic_vector(34 downto 0);
	
begin
	Inst_falling_edge_sync: falling_edge_sync PORT MAP(
		signal_in => signal_in,
		clk => clk,
		edge_detected => sig1(0) 
	);

	Inst_rising_edge_sync: rising_edge_sync PORT MAP(
		signal_in => signal_in,
		clk => clk,
		edge_detected => sig1(1)
	);

-- MUX1 for syncronization
process(sig1,sig3(1))
	begin
	   case (sig1) is 
      when "01" =>
         sig3(0) <= '1';
      when "10" =>
         sig3(0) <= '0';
      when others =>
         sig3(0) <= sig3(1);
   end case;
end process;

-- delay chain

delay_chain: for i in 0 to 15 generate
   process(reset, clk, sig3)
   begin		
      if reset = '1' then
		    sig3(i+1) <= '0';
      elsif (clk'event and clk='1') then
	       sig3(i+1) <= sig3(i);
      end if;
   end process;
end generate;




-- Mux to select delayed signal
   signal_sync_delayed_0_mux : Mux32_bit
		port map (
			M => sig3(31 downto 0),
			S => set_delay(4 downto 0),
			O => signal_sync_delayed_0);

-- also using mux to prallize signals
-- Mux to select delayed signal
   signal_sync_delayed_1_mux : Mux32_bit
		port map (
			M => sig3(32 downto 1),
			S => set_delay(4 downto 0),
			O => signal_sync_delayed_1);

-- Mux to select delayed signal
   signal_sync_delayed_2_mux : Mux32_bit
		port map (
			M => sig3(33 downto 2),
			S => set_delay(4 downto 0),
			O => signal_sync_delayed_2);

-- Mux to select delayed signal
   signal_sync_delayed_3_mux : Mux32_bit
		port map (
			M => sig3(34 downto 3),
			S => set_delay(4 downto 0),
			O => signal_sync_delayed_3);

end Behavioral;