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-- You must compile the wrapper file MUX_64times1Bit_to1Bit.vhd when simulating
-- the core, MUX_64times1Bit_to1Bit. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY MUX_64times1Bit_to1Bit IS
	port (
	M: IN std_logic_VECTOR(63 downto 0);
	S: IN std_logic_VECTOR(5 downto 0);
	O: OUT std_logic);
END MUX_64times1Bit_to1Bit;

ARCHITECTURE MUX_64times1Bit_to1Bit_a OF MUX_64times1Bit_to1Bit IS
-- synthesis translate_off
component wrapped_MUX_64times1Bit_to1Bit
	port (
	M: IN std_logic_VECTOR(63 downto 0);
	S: IN std_logic_VECTOR(5 downto 0);
	O: OUT std_logic);
end component;

-- Configuration specification 
	for all : wrapped_MUX_64times1Bit_to1Bit use entity XilinxCoreLib.C_MUX_BIT_V7_0(behavioral)
		generic map(
			c_has_aset => 0,
			c_sync_priority => 1,
			c_has_sclr => 0,
			c_height => 0,
			c_enable_rlocs => 1,
			c_sel_width => 6,
			c_latency => 0,
			c_ainit_val => "0",
			c_has_ce => 0,
			c_pipe_stages => 0,
			c_has_aclr => 0,
			c_sync_enable => 0,
			c_has_ainit => 0,
			c_sinit_val => "0",
			c_has_sset => 0,
			c_has_sinit => 0,
			c_has_q => 0,
			c_has_o => 1,
			c_inputs => 64);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_MUX_64times1Bit_to1Bit
		port map (
			M => M,
			S => S,
			O => O);
-- synthesis translate_on

END MUX_64times1Bit_to1Bit_a;