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#
# Xilinx Core Generator version J.36
# Date: Sun May 11 19:49:52 2008
#
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#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
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#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc3s500e
SET devicefamily = spartan3e
SET flowvendor = Foundation_iSE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = pq208
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = True
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT FD-based_Parallel_Register family Xilinx,_Inc. 7.0
# END Select
# BEGIN Parameters
CSET async_init_value=0
CSET asynchronous_settings=none
CSET ce_overrides=sync_controls_override_ce
CSET clock_enable=true
CSET component_name=LATCH_6Bit
CSET create_rpm=true
CSET data_width=6
CSET set_clear_priority=clear_overrides_set
CSET sync_init_value=0
CSET synchronous_settings=clear
# END Parameters
GENERATE
# CRC: afe3be97