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-- You must compile the wrapper file LATCH_6Bit.vhd when simulating
-- the core, LATCH_6Bit. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY LATCH_6Bit IS
	port (
	D: IN std_logic_VECTOR(5 downto 0);
	Q: OUT std_logic_VECTOR(5 downto 0);
	CLK: IN std_logic;
	CE: IN std_logic;
	SCLR: IN std_logic);
END LATCH_6Bit;

ARCHITECTURE LATCH_6Bit_a OF LATCH_6Bit IS
-- synthesis translate_off
component wrapped_LATCH_6Bit
	port (
	D: IN std_logic_VECTOR(5 downto 0);
	Q: OUT std_logic_VECTOR(5 downto 0);
	CLK: IN std_logic;
	CE: IN std_logic;
	SCLR: IN std_logic);
end component;

-- Configuration specification 
	for all : wrapped_LATCH_6Bit use entity XilinxCoreLib.C_REG_FD_V7_0(behavioral)
		generic map(
			c_width => 6,
			c_has_sinit => 0,
			c_sinit_val => "000000",
			c_has_ce => 1,
			c_ainit_val => "000000",
			c_sync_enable => 0,
			c_has_aset => 0,
			c_enable_rlocs => 1,
			c_has_aclr => 0,
			c_has_sset => 0,
			c_sync_priority => 1,
			c_has_ainit => 0,
			c_has_sclr => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_LATCH_6Bit
		port map (
			D => D,
			Q => Q,
			CLK => CLK,
			CE => CE,
			SCLR => SCLR);
-- synthesis translate_on

END LATCH_6Bit_a;