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#
# Xilinx Core Generator version J.36
# Date: Sun May 11 19:49:28 2008
#
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#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
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#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc3s500e
SET devicefamily = spartan3e
SET flowvendor = Foundation_iSE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = pq208
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = True
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Binary_Counter family Xilinx,_Inc. 8.0
# END Select
# BEGIN Parameters
CSET aclr=true
CSET ainit=false
CSET ainit_value=0
CSET aset=false
CSET async_threshold_output=false
CSET ce=true
CSET component_name=Counter_6Bit
CSET count_mode=UP
CSET cycle_early_threshold_output=false
CSET final_count_value=1
CSET increment_value=1
CSET load=false
CSET load_ce_priority=CE_Overrides_Load
CSET output_width=6
CSET restrict_count=false
CSET sclr=false
CSET sinit=false
CSET sinit_value=0
CSET sset=false
CSET sync_ce_priority=Sync_Overrides_CE
CSET sync_threshold_output=false
CSET syncctrlpriority=Reset_Overrides_Set
CSET threshold_value=1
# END Parameters
GENERATE
# CRC: ca648d7b