##############################################################
#
# Xilinx Core Generator version J.36
# Date: Sun Apr 20 10:39:44 2008
#
##############################################################
#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc3s500e
SET devicefamily = spartan3e
SET flowvendor = Foundation_iSE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = pq208
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = True
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Adder_Subtracter family Xilinx,_Inc. 7.0
# END Select
# BEGIN Parameters
CSET async_init_value=0
CSET asynchronous_settings=none
CSET bypass=false
CSET bypass_sense=active_high
CSET carry_borrow_input=false
CSET carry_borrow_output=false
CSET ce_override_for_bypass=true
CSET ce_overrides=sync_controls_override_ce
CSET clock_enable=false
CSET component_name=ALU_adder
CSET create_rpm=true
CSET latency=0
CSET operation=add
CSET output_options=non_registered
CSET output_width=48
CSET overflow_output=false
CSET port_a_sign=unsigned
CSET port_a_width=6
CSET port_b_constant=false
CSET port_b_constant_value=0
CSET port_b_sign=unsigned
CSET port_b_width=48
CSET set_clear_priority=clear_overrides_set
CSET sync_init_value=0
CSET synchronous_settings=none
# END Parameters
GENERATE
# CRC: 70250373