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-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:43:06 04/17/2008 
-- Design Name: 
-- Module Name:    LUT_emulation - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity LUT_emulation is
    Port ( clk40 : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           LUT_data_out : out  STD_LOGIC_VECTOR (3 downto 0));
end LUT_emulation;

architecture Behavioral of LUT_emulation is

component clk_counter
	port (
	clk: IN std_logic;
	q: OUT std_logic_VECTOR(24 downto 0));
end component;

-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of clk_counter: component is true;

signal q: std_logic_vector(24 downto 0);
signal LUT_data_out_signal : std_logic_vector(3 downto 0);

begin

inst1_clk_counter : clk_counter
		port map (
			clk => clk40,
			q(24 downto 0) => q(24 downto 0));
			
process(q)
begin
   if q(7 downto 0) = X"00" then
	   LUT_data_out_signal <= "1111";
	else
	   LUT_data_out_signal <= "1100";
	end if;
end process;

process(clk40, reset, LUT_data_out_signal)
begin
   if reset = '1' then
	   LUT_data_out <= "0000";
	elsif clk40'event and clk40 = '1' then
	   LUT_data_out <= LUT_data_out_signal;
	end if;
end process;

--LUT_data_out(3 downto 1) <= "000";
--LUT_data_out(0) <= q(0);
--LUT_data_out(1) <= q(0);
--LUT_data_out(2) <= q(0);
--LUT_data_out(3) <= q(0);
-- LUT_data_out <= "1100"; 
end Behavioral;