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-- Company: 
-- Engineer: 
-- 
-- Create Date:    09:50:17 05/30/2008 
-- Design Name: 
-- Module Name:    FEB_emulator - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity FEB_emulator is
    Port ( clk160 : in STD_LOGIC;
	        clk80 : in  STD_LOGIC;
			  clk40 : in STD_LOGIC;
	        reset : in STD_LOGIC;
           pattern1 : in  STD_LOGIC_VECTOR (1 downto 0);
           pattern2 : in  STD_LOGIC_VECTOR (1 downto 0);
           pat1_per_pat2 : in  STD_LOGIC_VECTOR (15 downto 0);
           enable : in  STD_LOGIC;
			  output : out STD_LOGIC;
			  rising_edge_marker_reg : in STD_LOGIC);
end FEB_emulator;

architecture Behavioral of FEB_emulator is

signal counter : std_logic_vector(1 downto 0);
signal rate_counter : std_logic_vector(15 downto 0);
signal sig1, sig3, sig4, sig5 : std_logic;
signal sig2 : std_logic_vector(1 downto 0);
signal rising_edge_marker : std_logic;

begin
-- register the rising edge_marker for better timing
process(reset,clk160, rising_edge_marker)
begin
   if reset = '1' then
	   rising_edge_marker <= '0';
	elsif clk160'event and clk160 = '0' then
	   rising_edge_marker <= rising_edge_marker_reg;
	end if;
end process;

process(clk80, reset, counter, rising_edge_marker)
begin
   if reset = '1' then
	   counter <= "00";
	elsif clk80'event and clk80 = '1' then
	   if rising_edge_marker = '1' then
		   counter <= "00";
		else
	      counter <= counter + '1';
		end if;
	end if;
end process;

process(clk40, reset, rate_counter, sig5)
begin
   if reset = '1' then
	   rate_counter <= X"0000" ;
	elsif clk80'event and clk80 = '1' then
	   if sig5 = '1' then
		   rate_counter <= X"0000";
		else
		   rate_counter <= rate_counter + '1';
		end if;
	end if;
end process;

-- information comes only with clk40
sig1 <= '1' when rate_counter(15 downto 1) = pat1_per_pat2(15 downto 0)  else '0';

process(clk40, reset, sig1)
begin
   if reset = '1' then
	    sig5 <= '0';
	elsif clk40'event and clk40 = '0' then
	    sig5 <= sig1;
	end if;
end process;

-- switch between patterns
process(sig1, pattern1, pattern2)
begin
   case sig1 is
	   when '0' =>
		   sig2 <= pattern1;
		when '1' =>
		   sig2 <= pattern2;
		when others =>
		   sig2 <= pattern1;
	end case;
end process;

-- serialize
process(sig2, counter(0))
begin
   case counter(0) is
	   when '0' =>
		   sig3 <= sig2(0);
		when '1' =>
		   sig3 <= sig2(1);
		when others =>
		   sig3 <= sig2(0);
	end case;
end process;

-- if not enabled the output signal is 0
sig4 <= sig3 and enable;

process(clk80, reset, sig4)
begin
   if reset = '1' then
	   output <= sig4;
	elsif clk80'event and clk80 = '1' then
	   output <= sig4;
	end if;
end process;

end Behavioral;