----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:32:15 03/30/2008 
-- Design Name: 
-- Module Name:    trigger_flash - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity trigger_flash is
    Port ( puls : in  STD_LOGIC;
	        clk : in STD_LOGIC;
			  reset : in STD_LOGIC;
           flash : out  STD_LOGIC);
end trigger_flash;

architecture Behavioral of trigger_flash is

signal puls_traped: std_logic;
signal reset_puls_traped_signal: std_logic;
signal counter: integer range 0 to 16777215;

begin

-- puls trap
process(clk,reset,puls, reset_puls_traped_signal)
begin
   if (reset = '1' or reset_puls_traped_signal = '1') then
	   puls_traped <= '0';
	elsif(puls'event and puls = '1') then
	   puls_traped <= '1';
   end if;
end process;

-- puls trap reset counter
process(clk, counter, puls_traped)
begin
   if (reset = '1' or puls_traped = '0') then
	   counter <= 0;
   elsif(clk'event and clk='1') then
	   counter <= counter + 1;
	end if;
end process;

-- reset comperator
process(counter)
begin
   if counter = 16777215 then -- 0.41 seconds = 16777215
	   reset_puls_traped_signal <= '1';
	else
	   reset_puls_traped_signal <= '0';
	end if;
end process;

flash <= puls_traped;

end Behavioral;