---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 20:03:05 04/05/2008 -- Design Name: -- Module Name: timing_analyze_module - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity timing_analyze_module is Port ( activate : in STD_LOGIC; -- keep active high whenever you want to be sensitive for triggers reset : in STD_LOGIC; -- normal sync reset design reset clear : in STD_LOGIC; -- clears the done; next activate will start recording done : out STD_LOGIC; signals : in STD_LOGIC_VECTOR (31 downto 0); clk : in STD_LOGIC; clk_scsn : in STD_LOGIC; readout_value : out STD_LOGIC_VECTOR (31 downto 0); readout_address : in STD_LOGIC_VECTOR (8 downto 0); trigger_mask: in STD_LOGIC_VECTOR(31 downto 0)); -- mark the bits you want to use for triggering with 1 end timing_analyze_module; architecture Behavioral of timing_analyze_module is signal sig1, sig1_reg, sig7, sig9, sig10, sig11, sig12: std_logic_vector(31 downto 0); signal sig2, sig3, sig4, sig5, sig8: std_logic; signal counter: std_logic_vector(8 downto 0); signal clear_signal: std_logic; signal done_signal: std_logic; type type_signals_reg is array (0 to 9) of std_logic_vector(31 downto 0); signal signals_reg : type_signals_reg; signal comp : std_logic_vector(10 downto 0); begin clear_signal <= clear or reset; -- trigger logic: start if one of the trigger signals changes -- detect signal change trigger_chain: for i in 0 to 31 generate process(reset, clk, signals(i)) begin if reset = '1' then sig7(i) <= '0'; elsif (clk'event and clk='1') then sig7(i) <= signals(i); end if; end process; process(reset, clk, sig12(i)) begin if reset = '1' then sig9(i) <= '0'; elsif (clk'event and clk='1') then sig9(i) <= sig12(i); end if; end process; process(reset, clk, sig11(i)) begin if reset = '1' then sig10(i) <= '0'; elsif (clk'event and clk='1') then sig10(i) <= sig11(i); end if; end process; sig1(i) <= ((sig7(i) xor sig9(i)) and trigger_mask(i)); -- after a clear prevent the trigger from being started by an old change -- set all registers to the signal value if there is a reset sig11(i) <= sig9(i) when clear_signal = '0' else signals(i); sig12(i) <= sig7(i) when clear_signal = '0' else signals(i); end generate; -- trigger comperator don't use --sig2 <= '1' when sig1 /= X"00000000" else '0'; -- due to timing problems in the clk160 domain -- use pipeline structure for the comparison because of timing issues -- in each pipelinestep one LUT (4 inputs 1 output) -- this costs a view presamples process(clk, reset, sig1) begin if reset = '1' then sig1_reg <= X"00000000"; elsif clk'event and clk = '1' then sig1_reg <= sig1; end if; end process; -- 1st pipeline step process(clk, reset, sig1_reg(3 downto 0)) begin if reset = '1' then comp(0) <= '0'; elsif clk'event and clk = '1' then if sig1_reg(3 downto 0) /= "0000" then comp(0) <= '1'; else comp(0) <= '0'; end if; end if; end process; process(clk, reset, sig1_reg(7 downto 4)) begin if reset = '1' then comp(1) <= '0'; elsif clk'event and clk = '1' then if sig1_reg(7 downto 4) /= "0000" then comp(1) <= '1'; else comp(1) <= '0'; end if; end if; end process; process(clk, reset, sig1_reg(11 downto 8)) begin if reset = '1' then comp(2) <= '0'; elsif clk'event and clk = '1' then if sig1_reg(11 downto 8) /= "0000" then comp(2) <= '1'; else comp(2) <= '0'; end if; end if; end process; process(clk, reset, sig1_reg(15 downto 12)) begin if reset = '1' then comp(3) <= '0'; elsif clk'event and clk = '1' then if sig1_reg(15 downto 12) /= "0000" then comp(3) <= '1'; else comp(3) <= '0'; end if; end if; end process; process(clk, reset, sig1_reg(19 downto 16)) begin if reset = '1' then comp(4) <= '0'; elsif clk'event and clk = '1' then if sig1_reg(19 downto 16) /= "0000" then comp(4) <= '1'; else comp(4) <= '0'; end if; end if; end process; process(clk, reset, sig1_reg(23 downto 20)) begin if reset = '1' then comp(5) <= '0'; elsif clk'event and clk = '1' then if sig1_reg(23 downto 20) /= "0000" then comp(5) <= '1'; else comp(5) <= '0'; end if; end if; end process; process(clk, reset, sig1_reg(27 downto 24)) begin if reset = '1' then comp(6) <= '0'; elsif clk'event and clk = '1' then if sig1_reg(27 downto 24) /= "0000" then comp(6) <= '1'; else comp(6) <= '0'; end if; end if; end process; process(clk, reset, sig1_reg(31 downto 28)) begin if reset = '1' then comp(7) <= '0'; elsif clk'event and clk = '1' then if sig1_reg(31 downto 28) /= "0000" then comp(7) <= '1'; else comp(7) <= '0'; end if; end if; end process; -- 2nd pipeline step process(clk, reset, comp(3 downto 0)) begin if reset = '1' then comp(8) <= '0'; elsif clk'event and clk = '1' then comp(8) <= comp(0) or comp(1) or comp(2) or comp(3); end if; end process; process(clk, reset , comp(3 downto 0)) begin if reset = '1' then comp(9) <= '0'; elsif clk'event and clk = '1' then comp(9) <= comp(4) or comp(5) or comp(6) or comp(7); end if; end process; -- 3rd pipeline step process(clk, reset, comp(9 downto 8)) begin if reset = '1' then sig2 <= '0'; elsif clk'event and clk = '1' then sig2 <= comp(9) or comp(8); end if; end process; --trigger trap sig8 <= sig2 and activate; sig3 <= sig8 or sig5; process(sig3,sig4,clk, reset) begin if sig4 ='1' then sig5 <= '0'; elsif clk'event and clk = '1' then sig5 <= sig3; end if; end process; sig4 <= done_signal or clear_signal; -- memory address counter process(clk, reset, counter, clear_signal, sig5) begin if clear_signal = '1' then counter <= "000000000"; elsif clk'event and clk='1' and sig5 = '1' then counter <= counter + '1'; end if; end process; -- stop recording if memory is full done_signal <= '1' when counter = 511 else '0'; -- buffer for presamples signals_reg(0) <= sig10(31 downto 0); presamples: for jj in 1 to 9 generate process(reset, clk, signals_reg(jj-1)) begin if reset = '1' then signals_reg(jj) <= X"00000000"; elsif clk'event and clk='1' then signals_reg(jj) <= signals_reg(jj-1); end if; end process; end generate; -- memory to store counter value and trigger pattern RAMB16_S36_S36_inst : RAMB16_S36_S36 generic map ( INIT_A => X"000000000", -- Value of output RAM registers on Port A at startup INIT_B => X"000000000", -- Value of output RAM registers on Port B at startup SRVAL_A => X"000000000", -- Port A ouput value upon SSR assertion SRVAL_B => X"000000000", -- Port B ouput value upon SSR assertion WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE SIM_COLLISION_CHECK => "NONE", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" -- The following INIT_xx declarations specify the initial contents of the RAM -- Address 0 to 127 INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", -- Address 128 to 255 INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", -- Address 256 to 383 INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", -- Address 384 to 511 INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", -- The next set of INITP_xx are for the parity bits -- Address 0 to 127 INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", -- Address 128 to 255 INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", -- Address 256 to 383 INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", -- Address 384 to 511 INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000") port map ( DOA => open, -- Port A 32-bit Data Output DOB => readout_value, -- Port B 32-bit Data Output DOPA => open, -- Port A 4-bit Parity Output DOPB => open, -- Port B 4-bit Parity Output ADDRA => counter, -- Port A 9-bit Address Input ADDRB => readout_address, -- Port B 9-bit Address Input CLKA => clk, -- Port A Clock CLKB => clk_scsn, -- Port B Clock DIA => signals_reg(9),--sig10(31 downto 0), -- Port A 32-bit Data Input DIB => X"00000000", -- Port B 32-bit Data Input DIPA => X"0", -- Port A 4-bit parity Input DIPB => X"0", -- Port-B 4-bit parity Input ENA => '1', -- Port A RAM Enable Input ENB => '1', -- PortB RAM Enable Input SSRA => reset, -- Port A Synchronous Set/Reset Input SSRB => reset, -- Port B Synchronous Set/Reset Input WEA => sig5, -- Port A Write Enable Input WEB => '0' -- Port B Write Enable Input ); done <= done_signal; end Behavioral;